Decomposition-based logic synthesis for PAL-based CPLDs

Opara, Adam; Kania, Dariusz

doi:10.2478/v10006-010-0027-1

Cited by 30 publications

(15 citation statements)

References 22 publications

(23 reference statements)

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“…It should be noted that in the most cases, a significant reduction in logic levels together with a smaller reduction of logic cells was observed. More experimental results were presented in [11,12,13,14,15,16,17,18,19,20,23].…”

Section: Resultsmentioning

confidence: 99%

“…Much more rarely is logic synthesis dedicated for other types of programmable devices executed. Some synthesis algorithms dedicated for PLA structures are known [10,13,14,23,33,41,42]. In some other methods, decomposition algorithms developed for LUT-based FPGAs were directly adapted to other programmable logic device architectures [2,8].…”

Section: Classical Design Flowmentioning

confidence: 99%

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Finite State Machine Logic Synthesis for Complex Programmable Logic Devices

Czerwiński

Kania

2013

Lecture Notes in Electrical Engineering

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Section: Resultsmentioning

confidence: 99%

Section: Classical Design Flowmentioning

confidence: 99%

Finite State Machine Logic Synthesis for Complex Programmable Logic Devices

Czerwiński

Kania

2013

Lecture Notes in Electrical Engineering

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“…A classic model of decomposition may also be one of the elements of synthesis dedicated to CPLD structures [18][19][20]. In fact, it is the basis of function synthesis reflected in LUT-based FPGA structures.…”

Section: Decomposition Of Multi-output Functions Orientedmentioning

confidence: 99%

“…The problem may be solved by creating equivalence classes and analyzing the consistency in a graph's structure [41,42]. The process of searching for equivalence classes in one-root graphs is as described in [20,42].…”

Section: Decomposition Of Multi-output Functions Oriented To Configurmentioning

confidence: 99%

Decomposition of multi-output functions oriented to configurability of logic blocks

Kubica

Kania

2017

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. The main goal of the paper is to present a logic synthesis strategy dedicated to an LUT-based FPGA. New elements of the proposed synthesis strategy include: an original method of function decomposition, non-disjoint decomposition, and technology mapping dedicated to configurability of logic blocks. The aim of all of the proposed synthesis approaches is the sharing of appropriately configured logic blocks. Innovation of the methods is based on the way of searching decomposition, which relies on multiple cutting of an MTBDD diagram describing a multi-output function. The essence of the proposed algorithms rests on the method of unicoding dedicated to sharing resources, searching non-disjoint decomposition on the basis of the partition of root tables, and choosing the levels of diagram cutting that will guarantee the best mapping to complex logic blocks. The methods mentioned above were implemented in the MultiDec tool. The efficiency of the analyzed methods was experimentally confirmed by comparing the synthesis results with both academic and commercial tools.Key words: BDD, decomposition, logic synthesis, technology mapping. Decomposition of multi-output functions orientedto configurability of logic blocks There are the methods of function technology mapping in LUT-based FPGA structures in which a classic model of decomposition plays a crucial role. A classic model of decomposition may also be one of the elements of synthesis dedicated to CPLD structures [18][19][20]. In fact, it is the basis of function synthesis reflected in LUT-based FPGA structures. Sometimes, logic synthesis method is targeted at FPGA architectures with specialized embedded memory blocks (EMB) [21,22]. In all cases, decomposition of Boolean functions turns out to be a key problem. Decomposition of multi-output functions leads to better results than decomposition done separately on each single function. It is because of the fact that shared blocks are the result of decomposition of Boolean functions and are used by several single-output functions at the same time. A classic model of decomposition is the basis of a series of decomposition algorithms [5,[23][24][25]. Synthesis methods use various graph algorithms that enable indication of column multiplicity of partition tables or a proper transformation of Boolean functions. Undoubtedly, one of the main advantages of a classic function decomposition is the natural admitting of don't-care states. It is probably the most important element making these methods one of the most effective. In last years, a series of various synthesis

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“…Moreover, BDDs can be easily used for function representation of multi-output functions (Sasao and Butler, 1996). As a result of all these advantages, the BDD has been often used in tools that supported the process of synthesis such as the BDS (Yang and Ciesielski, 2002), the DDBDD (Cheng et al, 2007), and dekBDD (Opara and Kania, 2010). The essence of using BDDs in the process of synthesis dedicated to FPGA structures has been presented by Scholl (2001).…”

Section: Introductionmentioning

confidence: 99%

Area–Oriented Technology Mapping for LUT–Based Logic Blocks

Kubica

Kania

2017

International Journal of Applied Mathematics and Computer Science

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One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

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Decomposition-based logic synthesis for PAL-based CPLDs

Cited by 30 publications

References 22 publications

Finite State Machine Logic Synthesis for Complex Programmable Logic Devices

Finite State Machine Logic Synthesis for Complex Programmable Logic Devices

Decomposition of multi-output functions oriented to configurability of logic blocks

Area–Oriented Technology Mapping for LUT–Based Logic Blocks

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