Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture

Kwon, Young–Se; Yang, Jung‐Seok; Cho, Yongcheol Peter; Shin, Kyoung-Seon; Chung, Jaehoon; Han, Jinho; Lyuh, Chun‐Gi; Kim, Hyun-Mi; Kim, Chan; Choi, Minseok

doi:10.1109/aicas.2019.8771603

Cited by 12 publications

(4 citation statements)

References 7 publications

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“…In addition, we use a watchdog [11] to prevent a system crash in case that the STC interrupt is not generated or handled within a predefined time.…”

Section: Evaluation Resultsmentioning

confidence: 99%

A layer‐wise frequency scaling for a neural processing unit

et al. 2022

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Dynamic voltage frequency scaling (DVFS) has been widely adopted for runtime power management of various processing units. In the case of neural processing units (NPUs), power management of neural network applications is required to adjust the frequency and voltage every layer to consider the power behavior and performance of each layer. Unfortunately, DVFS is inappropriate for layer-wise run-time power management of NPUs due to the long latency of voltage scaling compared with each layer execution time. Because the frequency scaling is fast enough to keep up with each layer, we propose a layerwise dynamic frequency scaling (DFS) technique for an NPU. Our proposed DFS exploits the highest frequency under the power limit of an NPU for each layer. To determine the highest allowable frequency, we build a power model to predict the power consumption of an NPU based on a real measurement on the fabricated NPU. Our evaluation results show that our proposed DFS improves frame per second (FPS) by 33% and saves energy by 14% on average, compared with DVFS.

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“…In addition, we use a watchdog [11] to prevent a system crash in case that the STC interrupt is not generated or handled within a predefined time.…”

Section: Evaluation Resultsmentioning

confidence: 99%

A layer‐wise frequency scaling for a neural processing unit

et al. 2022

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“…We have presented the accelerator model on the basis of the architecture presented in [24] as the baseline. However, the baseline architecture was modified according to the proposed buffer, datapath, and data control in Section.…”

Section: Experimental Environmentmentioning

confidence: 99%

Automated optimization for memory‐efficient high‐performance deep neural network accelerators

2020

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The increasing size and complexity of deep neural networks (DNNs) necessitate the development of efficient high‐performance accelerators. An efficient memory structure and operating scheme provide an intuitive solution for high‐performance accelerators along with dataflow control. Furthermore, the processing of various neural networks (NNs) requires a flexible memory architecture, programmable control scheme, and automated optimizations. We first propose an efficient architecture with flexibility while operating at a high frequency despite the large memory and PE‐array sizes. We then improve the efficiency and usability of our architecture by automating the optimization algorithm. The experimental results show that the architecture increases the data reuse; a diagonal write path improves the performance by 1.44× on average across a wide range of NNs. The automated optimizations significantly enhance the performance from 3.8× to 14.79× and further provide usability. Therefore, automating the optimization as well as designing an efficient architecture is critical to realizing high‐performance DNN accelerators.

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“…To achieve high computational throughput for processing AI algorithms, the AI processor has an STC with a multi-core architecture. The STC comprises 128 × 128 processing cores called NCs [15]. The processing core operates at 1.2 GHz.…”

Section: Many-core Architecturementioning

confidence: 99%

40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D

2020

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The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function‐safe architecture is proposed for a fault‐tolerance system such as an electronics system for autonomous cars. The general‐purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self‐recovering cache and dynamic lockstep function. The function‐safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28‐nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function‐safe design can have ISO26262 ASIL‐D with the single‐point fault‐tolerance rate of 99.64%.

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Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture

Cited by 12 publications

References 7 publications

A layer‐wise frequency scaling for a neural processing unit

A layer‐wise frequency scaling for a neural processing unit

Automated optimization for memory‐efficient high‐performance deep neural network accelerators

40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D

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