Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems

Flandre, Denis; Adriaensen, Stéphane; Akheyar, A.; Crahay, André; Demeûs, Laurent; Delatte, Pierre; Dessard, Vincent; Iñı́guez, Benjamı́n; Nève, Amaury; Katschmarskyj, Bohdan; Loumaye, Pierre; Laconte, J.; Martinez, Idellyse; Picun, Gonzalo; Rauly, E.; Renaux, Christian; Spote, David; Zitout, M; Dehan, M.; Parvais, B.; Simon, Pascal; Vanhoenacker, D.; Raskin, Jean‐Pierre

doi:10.1016/s0038-1101(01)00084-3

Cited by 87 publications

(29 citation statements)

References 32 publications

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“…Fully-depleted n-type SOl transistors were fabricated in a SOl wafer with doping concentration (NA) of 10 1 5 cm-3 and buried oxide thickness of 390 nm, with a 31 nm-thick gate oxide and a silicon layer with final thickness of 80 nm [8]. …”

Section: Device Characteristicsmentioning

confidence: 99%

Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors

Souza

Flandre²,

Pavanello

2013

28th Symposium on Microelectronics Technology and Devices (SBMicro 2013)

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This paper presents an experimental analysis of channel length influence on the analog characteristics of asymmetric self-cascode association of SOl transistors. It is shown that the increase of the drain current and transconductance is more pronounced with the reduction of the length of the transistor close to the source (L1), and, differently from the symmetric self casco de, suffers little influence of the length close to the drain (L2).On the contrary, the output conductance of symmetric and asymmetric threshold voltage structures is benefited by the increase of L2 and L/> although the asymmetric structure may offer a reduction of up to one order of magnitude in comparison to the symmetric one. It results in larger intrinsic voltage drain for asymmetric devices. This increase has shown to reach more than 20 dB for similar dimensions, or allow for dimension reduction without intrinsic gain degradation.

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Section: Device Characteristicsmentioning

confidence: 99%

Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors

Souza

Flandre²,

Pavanello

2013

28th Symposium on Microelectronics Technology and Devices (SBMicro 2013)

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“…The studied ULP diodes have been fabricated according to the fully-depleted SOI process described in (5), which features silicon film thickness (t Si ) of 80nm, and gate (t oxf ) and buried oxide (t oxb ) thickness of 31 nm and 390 nm, respectively. In all cases, transistors present channel length L=2μm and channel width W=100μm.…”

Section: Resultsmentioning

confidence: 99%

Performance of Ultra-Low-Power SOI CMOS Diodes Operating at Low Temperatures

Souza¹,

Rue²,

Flandre³

et al. 2011

ECS Trans.

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In this work the low temperature performance of ultra-low-power SOI CMOS diodes is presented. Experimental measurements performed in fabricated devices from 148K to 373K show that the temperature lowering can promote a significant leakage current reduction and increase of the forward current. Two-dimensional numerical simulations are used to extend the studied temperature range and analyze the doping concentration influence on the low temperature operation of these diodes.

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“…RF APPLICATIONS A variety of circuit design method, can be used to improve high temperature performance of microelectronics [8]. For analog applications, the stability of the circuit performance in terms of gain, matching, bandwidth, etc.…”

Section: Zero-temperature-coefficient Point Analysismentioning

confidence: 99%

Body-Biasing Control on Zero-Temperature-Coefficient in Partially Depleted SOI MOSFET

Kaamouchi¹,

Dambrine²,

Moussa³

et al. 2008

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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This work investigates the possibility to tune the Zero-Temperature-Coefficient (ZTC) points in partially depleted (PD) SOI nMOSFET technology by controlling the body-source forward bias (VBS). Measured transconductance and drain current in the saturation region at temperatures between 25 and 200 o C were observed for various body-source forward bias conditions. It is found that the variation of threshold voltage (VTH) with body bias has an influence on ZTC points. The measurement results show wide voltage-range of gate-voltage giving either the transconductance ZTC point (VGS,ZT Cg m ) or the drain-current ZTC point (VGS,ZT C I DS ), opening important opportunities in RF circuits design for high temperature applications.

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Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems

Cited by 87 publications

References 32 publications

Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors

Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors

Performance of Ultra-Low-Power SOI CMOS Diodes Operating at Low Temperatures

Body-Biasing Control on Zero-Temperature-Coefficient in Partially Depleted SOI MOSFET

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