Fully Automated, Testable Design of Fine-Grained Triple Mode Redundant Logic

Hindman, Nathan; Clark, Lawrence T.; Patterson, Dan W.; Holbert, Keith E.

doi:10.1109/tns.2011.2169280

Cited by 12 publications

(5 citation statements)

References 15 publications

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“…A cell library test chip [48] and the other test chips confirmed negligible I DD leakage increase (a few %) up to 2 Mrad(Si) [47] [46]. The caches have similar TID hardness, using annular NMOS transistors [40].…”

Section: Experimentally Measured Tid and Sel Hardnessmentioning

confidence: 79%

“…10 upper right). This allows an incorrect copy, whether brought into one of the D inputs or due to an SEU to be corrected in the low phase of the clock, when the slave feedback path is active [46]. The slave feedback is not in a critical timing path, so there is no impact on performance aside from the increased routing in TMR circuits.…”

Section: Tmr Self-correcting Flip-flopsmentioning

confidence: 99%

See 1 more Smart Citation

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

Clark

Patterson

Ramamurthy

et al. 2016

IEEE Trans. Comput.

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A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline are protected by microarchitecture approaches, i.e., the speculative pipeline is dual redundant, whereby instructions that have errors in one copy cause a pipeline restart-only matching results commit to architectural state. The register file is dual redundant with mechanisms for correction using one copy whose parity is correct. The data cache memory is write-through, allowing protection with parity. The remaining architectural state is protected via hardened circuits. These are implemented with self-correcting triple mode redundant (TMR) flip-flops and TMR logic. The design, implemented here on a 90-nm bulk CMOS process, achieves unprecedented single event effects hardness and 400+ MHz operating frequency at less than 500 mW power consumption. The main constituent circuit hardening approaches have been fabricated and tested separately. Broad beam testing of the constituent circuits has resulted in no uncorrectable soft errors below 100 MeV-cm 2 /mg LET EFF . We describe the CAD flows used to ensure node separation to achieve high immunity to multiple node charge collection and discuss the relative costs of the chosen hardening techniques.Index Terms-Radiation hardening by design (RHBD); microprocessor; cache memory; total ionizing dose; single event transients, soft error mitigation, single-event effects.

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Section: Experimentally Measured Tid and Sel Hardnessmentioning

confidence: 79%

Section: Tmr Self-correcting Flip-flopsmentioning

confidence: 99%

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

Clark

Patterson

Ramamurthy

et al. 2016

IEEE Trans. Comput.

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“…An important aspect of the rad-hard design with standard flip-flops is the compatibility with the design flow. Several previous approaches have proposed the modification of the design flow by introducing the processing of the synthesized design netlist, with the aim to convert the standard flip-flops into the TMR configurations [48]- [50]. Such an approach may be very exhaustive for a complex digital design with a large number of flip-flops.…”

Section: State-of-the-art Solutions For Rad-hard Flip-flopsmentioning

confidence: 99%

Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Schrape

Andjelković

Breitenreiter

et al. 2021

IEEE Trans. Circuits Syst. I

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Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard nonrad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130 nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV• cm 2 mg ) to (62.5 MeV• cm 2 mg ), depending on the variant.

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“…For the ASIC design of the hardened microprocessor HERMES [14], both DMR and TMR techniques were implemented, depending on which processor block was to be hardened, and the replicated redundancy domains were physically separated during the circuit layout design phase. Another approach in fine-grain techniques is the one proposed on [15], in which design flip-flops are replaced by self-correcting rad-hard by design (RHBD) flip-flops after synthesis, and triplication is performed on spatially separated regions during the placement phase. For FPGA designs, actions can be taken during the placement and routing implementation stages, such as inserting redundant routing connections [16] or using reliability-oriented place and route algorithms to physically separate the redundant copies and avoid single points of failure [17].…”

Section: Literature Surveymentioning

confidence: 99%

Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

et al. 2018

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Radiation effects can induce, amongst other phenomena, logic errors in digital circuits and systems. These logic errors corrupt the states of the internal memory elements of the circuits and can propagate to the primary outputs, affecting other onboard systems. In order to avoid this, Triple Modular Redundancy is typically used when full robustness against these phenomena is needed. When full triplication of the complete design is not required, selective hardening can be applied to the elements in which a radiation-induced upset is more likely to propagate to the main outputs of the circuit. The present paper describes a new approach for selectively hardening digital electronic circuits by design, which can be applied to digital designs described in the VHDL Hardware Description Language. When the designer changes the datatype of a signal or port to a hardened type, the necessary redundancy is automatically inserted. The automatically hardening features have been compiled into a VHDL package, and have been validated both in simulation and by means of fault injection.

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Fully Automated, Testable Design of Fine-Grained Triple Mode Redundant Logic

Cited by 12 publications

References 15 publications

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

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