Full System Emulation of Embedded Heterogeneous Multicores Based on QEMU

Chen, I-Hua; King, Chung-Ta; Chen, Yaohua; Lu, Juin-Ming

doi:10.1109/padsw.2018.8645045

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…Many research studies on dynamic translation methods have been published [11][12][13][14][15][16][17]. Dynamic translation frameworks, such as QEMU [17], are widely used in simulators, virtual machines, and disassemblers, effectively meeting the requirements of cross-architecture software migration.…”

Section: Overviewmentioning

confidence: 99%

A Dynamic and Static Binary Translation Method Based on Branch Prediction

Sun,

Wu,

et al. 2023

Electronics

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Binary translation is an important technique for achieving cross-architecture software migration. However, mainstream dynamic binary translation frameworks, such as QEMU, often generate a large amount of redundant code, which degrades the efficiency of the target code. To this end, we propose a dynamic–static binary translation method based on branch prediction. It first identifies parts of translation blocks following static branch prediction techniques. Then it translates these translation blocks into less-redundant native code blocks by canonical static translation algorithms. Finally, it executes all code blocks that are translated either statically or dynamically by correctly maintaining and switching their running contexts. In order to correctly weave the two types of translation activities, the proposed method only translates the next translation block that is data-independent from the current one by the active variable analysis algorithm, and records and shares the intermediate states of the dynamic and static translation activities via a carefully designed data structure. In particular, a shadow register-based context recovery mechanism is proposed to correctly record the running context of static translation blocks, and to correctly recover the context for dynamically translating and running blocks that were not statically translated. We also designed an adaptive memory optimization mechanism to dynamically release the memory of the mispredicted translation blocks. We implemented a dynamic–static binary translation framework by extending QEMU, called BP-QEMU (QEMU with branch prediction). We evaluated the translation correctness of BP-QEMU using the testing programs for the ARM and PPC instruction sets from QEMU, and evaluated the performance of BP-QEMU using the CoreMark benchmark code. The experimental results show that BP-QEMU can translate the instructions from the ARM and PPC architectures correctly; moreover, the average execution efficiency of the CoreMark code on BP-QEMU improves by 13.3% compared to that of QEMU.

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Section: Overviewmentioning

confidence: 99%

A Dynamic and Static Binary Translation Method Based on Branch Prediction

Sun,

Wu,

et al. 2023

Electronics

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“…In the mono-process approach used in [13,33], QEMU is included as a dynamic library in the virtual platform. Thus, the software emulator and the hardware simulator run in the same process, allowing the synchronization and communication mechanisms to be implemented as simple function calls.…”

Section: Background and Proposal Description 21 Hardware/software Cmentioning

confidence: 99%

Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

et al. 2021

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Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq−7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.

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NVMe-over-RPMsg: A Virtual Storage Device Model Applied to Heterogeneous Multi-Core SoCs

Zhang

Chen

2020

2020 10th Annual Computing and Communication Workshop and Conference (CCWC)

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Full System Emulation of Embedded Heterogeneous Multicores Based on QEMU

Cited by 3 publications

References 11 publications

A Dynamic and Static Binary Translation Method Based on Branch Prediction

A Dynamic and Static Binary Translation Method Based on Branch Prediction

Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

NVMe-over-RPMsg: A Virtual Storage Device Model Applied to Heterogeneous Multi-Core SoCs

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