A Dynamic and Static Binary Translation Method Based on Branch Prediction
Lianshan Sun,
Yanjin Wu,
Linxiangyi Li
et al.
Abstract:Binary translation is an important technique for achieving cross-architecture software migration. However, mainstream dynamic binary translation frameworks, such as QEMU, often generate a large amount of redundant code, which degrades the efficiency of the target code. To this end, we propose a dynamic–static binary translation method based on branch prediction. It first identifies parts of translation blocks following static branch prediction techniques. Then it translates these translation blocks into less-r… Show more
“…Peephole optimization is widely used in binary translation optimization [21,[26][27][28][29]. Bansal et al [21] utilized peephole optimization in rule-based binary translation.…”
Section: Related Workmentioning
confidence: 99%
“…Experimental results on the benchmark programs from the SPEC2006 benchmark suite show that an average 1.17× performance speedup can be achieved. Similarly, Sun et al [27] conducted peephole optimization on a static binary translator to eliminate redundant instructions. Rocha et al [28] integrated peephole optimization to optimize redundant memory access and fence instructions during the translation of concurrent programs.…”
Section: Related Workmentioning
confidence: 99%
“…DBT optimizations have been studied widely in the literature [8,27,[38][39][40][41]. Cota et al [8] enhanced FP emulation performance by surrounding the use of the host FP unit with a minimal amount of non-FP code and deferring corner cases to the slower soft-float code.…”
The emergence of new instruction set architectures (ISAs) poses challenges in ensuring compatibility with legacy applications. Dynamic binary translation (DBT) serves as a crucial approach for achieving cross-ISA compatibility, enabling legacy applications to run compatibly with cross-ISAs. However, software-based translation encounters significant performance overhead, including substantial memory access and insufficient exploitation of target architecture features. The significant performance overhead challenges hinder the practical implementation of DBT. In this paper, we investigate a novel peephole optimization approach. First, we perform peephole analysis to identify redundant memory access and suboptimal instruction sequences. Next, we leverage live variable analysis to eliminate redundant memory-access instructions. Additionally, we bridge the gaps between cross-ISAs by exploiting ISA-specific features through instruction fusion. Finally, we implement the proposed optimization design using the open-source QEMU and extensively evaluate it on both ARM64 and SW64 platforms. The experimental results reveal that SPEC2006 benchmark effectively gets a maximum performance speedup of 1.52×, alongside a reduction in code size of up to 13.98%. These results affirm the effectiveness of our optimization approach in DBT performance and code sizes.
“…Peephole optimization is widely used in binary translation optimization [21,[26][27][28][29]. Bansal et al [21] utilized peephole optimization in rule-based binary translation.…”
Section: Related Workmentioning
confidence: 99%
“…Experimental results on the benchmark programs from the SPEC2006 benchmark suite show that an average 1.17× performance speedup can be achieved. Similarly, Sun et al [27] conducted peephole optimization on a static binary translator to eliminate redundant instructions. Rocha et al [28] integrated peephole optimization to optimize redundant memory access and fence instructions during the translation of concurrent programs.…”
Section: Related Workmentioning
confidence: 99%
“…DBT optimizations have been studied widely in the literature [8,27,[38][39][40][41]. Cota et al [8] enhanced FP emulation performance by surrounding the use of the host FP unit with a minimal amount of non-FP code and deferring corner cases to the slower soft-float code.…”
The emergence of new instruction set architectures (ISAs) poses challenges in ensuring compatibility with legacy applications. Dynamic binary translation (DBT) serves as a crucial approach for achieving cross-ISA compatibility, enabling legacy applications to run compatibly with cross-ISAs. However, software-based translation encounters significant performance overhead, including substantial memory access and insufficient exploitation of target architecture features. The significant performance overhead challenges hinder the practical implementation of DBT. In this paper, we investigate a novel peephole optimization approach. First, we perform peephole analysis to identify redundant memory access and suboptimal instruction sequences. Next, we leverage live variable analysis to eliminate redundant memory-access instructions. Additionally, we bridge the gaps between cross-ISAs by exploiting ISA-specific features through instruction fusion. Finally, we implement the proposed optimization design using the open-source QEMU and extensively evaluate it on both ARM64 and SW64 platforms. The experimental results reveal that SPEC2006 benchmark effectively gets a maximum performance speedup of 1.52×, alongside a reduction in code size of up to 13.98%. These results affirm the effectiveness of our optimization approach in DBT performance and code sizes.
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