Full swing logic inverter with amorphous SiInZnO and GaInZnO thin film transistors

Debnath, Pulak Chandra; Lee, Sang Yeol

doi:10.1063/1.4747800

Cited by 33 publications

(17 citation statements)

References 14 publications

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“…Figure (a) shows the equivalent circuit of the fabricated depletion‐load‐type logic inverter. In the two inverters fabricated, the TFT devices in 4 mTorr N 2 having negative V th are commonly used in the depletion mode (D‐mode) . Each inverter used the enhancement mode (E‐mode) with different annealing atmospheres of either air or 2 mTorr N 2 .…”

Section: Resultsmentioning

confidence: 99%

Thin Film Logic Circuits with Amorphous SiInZnO Channel Layer Annealed at Different Atmospheres for Next‐Generation Integrated Circuits

Lee

2018

Physica Status Solidi (a)

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In this study, amorphous-oxide-based thin film logic circuits are fabricated using only an n-type silicon-indium-zinc-oxide (a-SIZO) active channel layer annealed at different atmospheres (N 2 or air). More carriers are present in the N 2 atmosphere than in the air because the number of oxygen vacancies (V O ) formed is higher. The inverters (NOT logic circuits) are simply fabricated by adopting different V th , adjusted by using different annealing atmospheres. The inverters have high voltage gain values of 11.64 and 9.99 at V DD ¼ 5 V. A higher gain is obtained when the thin film transistor annealed in N 2 is used in the enhancement mode. The reason for this is closely related to the subthreshold slope value. Furthermore, more complex n-type-based NAND and NOR thin-film circuits are fabricated by simply adopting different annealing atmospheres, and are confirmed to operate like the logic gates. This simple fabrication method of thin-film logic circuits can open up the possibility for the implementation of next-generation integrated circuits. Experimental SectionA staggered bottom-gate structure was used for the TFT structure, and a p-type silicon wafer with 200-nm SiO 2 (resistivity ¼ 0.001-0.002 Ω cm À1 ) was used as the substrate.

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Section: Resultsmentioning

confidence: 99%

Thin Film Logic Circuits with Amorphous SiInZnO Channel Layer Annealed at Different Atmospheres for Next‐Generation Integrated Circuits

Lee

2018

Physica Status Solidi (a)

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“…Therefore, the operating speed of CMOS logic was decreased due to the increase of input load capacitance. On the other hand, many researchers have studied to implement inverters by using only n‐type oxide TFTs to overcome poor p‐type oxide materials and for the simplicity of process . For instance, the E/D mode inverter with single ZnSnO (ZTO) and bulk accumulation inverter with uni‐layer amorphous‐InGaZnO (a‐IGZO) and bi‐layer a‐IGZO/InZnO (IZO) have been already demonstrated .…”

Section: Introductionmentioning

confidence: 99%

Full swing depletion-load inverter with amorphous SiZnSnO thin film transistors

Han

Lee

2016

Phys. Status Solidi A

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High performance inverter circuits consisting of 0.2 wt.% Si‐doped amorphous zinc‐tin‐oxide (a‐SZTO) thin film transistor (TFT) with depletion mode (D‐mode) and 0.5 and 2 wt.% Si‐doped a‐SZTO TFTs with enhancement mode (E‐mode) have been fabricated by using all n‐type metal‐oxide TFTs. These inverter models are operated by the difference of threshold voltage (Vth) between D‐mode and E‐mode simply controlled by changing Si‐doping ratio. High voltage gains of two inverters have been obtained ∼12 and ∼14.2 at VDD = 15 V and showed strongly depending on subthreshold swing (SS). It is possible to control the transition region and the noise margin of inverter circuits by changing SS and operating voltage (VOP) of E‐mode TFT.

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“…In this regards, n-channel unipolar as well as CMOS inverters have been explored recently. [8][9][10] Theoretically CMOS is the most ideal among various logic gate technologies in terms of power dissipation and performance, however, the lack of high-performance p-channel oxide devices hinders its development. For the unipolar approaches, the combination of a depletion-mode TFT as the load and an enhancement-mode TFT as the driver have been demonstrated to exhibit superior performance.…”

Section: Introductionmentioning

confidence: 99%

Novel InGaZnO inverters utilizing film profile engineering

Lin

Chan

et al. 2015

Jpn. J. Appl. Phys.

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In this study we cleverly employ the film profile engineering (FPE) concept to fabricate amorphous InGaZnO (a-IGZO) thin-film transistor (TFT)based inverters with a resistor-or transistor-load. In the fabrication the profiles of major thin films in both load and drive devices can be properly tailored with designed channel dimensions and deposition conditions. Although the inverter with a resistor-load is simpler in structure and fabrication, the switching performance is found to be restricted by the passive load component. The performance can be greatly promoted as a depletion-mode transistor-load is used instead. Full-swing operation is demonstrated for the inverter with a voltage gain of 28 recorded at an operation voltage (V DD ) of 5 V.

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Full swing logic inverter with amorphous SiInZnO and GaInZnO thin film transistors

Abstract: Articles you may be interested inThe effects of buffer layers on the performance and stability of flexible InGaZnO thin film transistors on polyimide substrates Appl. Phys. Lett.

Cited by 33 publications

References 14 publications

Thin Film Logic Circuits with Amorphous SiInZnO Channel Layer Annealed at Different Atmospheres for Next‐Generation Integrated Circuits

Thin Film Logic Circuits with Amorphous SiInZnO Channel Layer Annealed at Different Atmospheres for Next‐Generation Integrated Circuits

Full swing depletion-load inverter with amorphous SiZnSnO thin film transistors

Novel InGaZnO inverters utilizing film profile engineering

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