Full-Stack Memory Model Verification with TriCheck

Trippel, Caroline; Manerkar, Yatin A.; Lustig, Daniel; Pellauer, Michael; Martonosi, Margaret

doi:10.1109/mm.2018.032271062

Cited by 5 publications

(6 citation statements)

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“…Further, the framework automates deployments on MCUs with and without an FPU. Finally, [83] proposal enables ISA designers to iteratively refine and evaluate ISA specifications, allowing one to improve upon each result.…”

Section: ) Development Toolsmentioning

confidence: 99%

“…Trippel et al [83] propose a memory verification model to check for bugs on hardware and software memory models by providing a tool capable of verifying High-level Language (HLL), compilers, and ISAs uphold MCM requirements. Further, the authors uncovers potential inefficiencies of the RISC-V ISA specification and identifies possible solutions to mitigate these inefficiencies.…”

Section: ) Memory Modelmentioning

confidence: 99%

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A Survey of the RISC-V Architecture Software Support

et al. 2022

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RISC-V is a novel open instruction set architecture that supports multiple platforms while maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has been increasing in the last years, given that popular tool-chains and operating systems already have support for RISC-V. However, although many works have been exploring the RISC-V software ecosystem, no work that raised the current state of software support for RISC-V is available. In this context, this survey reviews the contributions introduced in the last years to understand the RISC-V's software ecosystem and its usage in both academic and industrial environments. We classified and evaluated the works into four main categories: fields of application, RISC-V implementations, software architecture, and deployment features. The primary goal of this research is to provide the community with a comprehensive overview of the current state of the art of RISC-V software support and identify and highlight the main contributions of recent works.

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Section: ) Development Toolsmentioning

confidence: 99%

Section: ) Memory Modelmentioning

confidence: 99%

A Survey of the RISC-V Architecture Software Support

et al. 2022

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“…The "PipeCheck" framework of Lustig, Martonosi et al [67,71,95,96] is designed to validate that processors faithfully implement their intended memory model, using a detailed pipeline semantics based on an axiomatic specification. Given that our approach has an underlying link to the behaviour of pipelines it may be possible to extend our framework so that it can make use of those existing tools for processor validation.…”

Section: Related Workmentioning

confidence: 99%

Parallelized sequential composition, pipelines, and hardware weak memory models

Colvin

2021

Preprint

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Since the introduction of the CDC 6600 in 1965 and its "scoreboarding" technique processors have not (necessarily) executed instructions in program order. Programmers of highlevel code may sequence independent instructions in arbitrary order, and it is a matter of significant programming abstraction and computational efficiency that the processor can be relied upon to make sensible parallelizations/reorderings of low-level instructions to take advantage of, for instance, multiple arithmetic units. At the architectural level such reordering is typically implemented via a per-processor pipeline, into which instructions are fetched in order, but possibly committed out of order depending on local considerations, provided any reordering preserves sequential semantics from that processor's perspective. However, multiprocessing and multicore architectures, where several pipelines run in parallel, can expose these processor-level reorderings as unexpected, or "weak", behaviours. Such weak behaviours are hard to reason about, and (via speculative execution) underlie at least one class of widespread security vulnerability.In this paper we introduce a novel program operator, parallelized sequential composition, which can be instantiated with a function that controls the reordering of atomic instructions. The operator generalises both standard sequential composition and parallel composition, and when appropriately instantiated exhibits many of the weak behaviours of the well-known hardware weak memory models TSO, Release Consistency, ARM, and RISC-V. We show that the use of this program-level operator is equivalent to sequential execution with reordering via a pipeline. Encoding reordering as a programming language operator admits the application of established compositional techniques (such as Owicki-Gries) for reasoning about weak behaviours, and is convenient for abstractly expressing properties from the literature such as sequential consistency. The semantics and theory is encoded and verified in the Isabelle/HOL theorem prover, and we give an implementation of the pipeline semantics in the Maude rewriting engine and use it empirically to show conformance of the semantics against established models of ARM and RISC-V, and elucidate some stereotypical weak behaviours from the literature.

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“…At time=31, a write-request due to St3 is issued to the L2 and the write is performed at the L2 at time=36. Because the lease for flag (35) would have expired, the L2 does not respond with a GWCT, and St3 completes at time=41. Meanwhile, at time=40, Ld1 attempts to read flag from the L1 but its lease would have expired at time=35.…”

Section: Consistency-directed Temporal Coherencementioning

confidence: 99%