A Primer on Memory Consistency and Cache Coherence

Nagarajan, Vijay; Sorin, Daniel J.; Hill, Mark D.; Wood, David

doi:10.1007/978-3-031-01764-3

Cited by 28 publications

(19 citation statements)

References 4 publications

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“…Cache policies. Caching has been well-studied for decades [47], [48], [49], [44], [50], [51]. Cache policies decide how to evict cache content upon cache overflows.…”

Section: Transactional Databasementioning

confidence: 99%

Competitive Consistent Caching for Transactions

Cao

Zhao

2022

2022 IEEE 38th International Conference on Data Engineering (ICDE)

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This paper studies cache policies for transactional caches. Different from conventional caches that focus on latency, transactional caches are primarily used to augment database systems and improve their transaction throughput by offloading read load onto the cache. A read transaction commits on the cache only if it is a consistent cache hit, i.e., all of its reads see a consistent view of the database. We prove that conventional cache policies are not competitive for transactions. We then show that for the large class of batching-based transaction systems, one can break the theoretical performance barrier of conventional cache policies via transaction consistency aware cache policies, although it is NP-complete to find the optimal ones. As a proof, we develop a consistent cache policy that is theoretically competitive under common cache schemes. To further exploit batching, we propose to reorder transactions within batches while guaranteeing that each transaction sees data values with bounded staleness. Using benchmarks and real-life workloads, we experimentally verify that our policy improves the transaction throughput of Memcached atop HBase by 126.95% on average, up to 479.27% higher than existing cache policies adopted for transactions.

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“…Cache policies. Caching has been well-studied for decades [47], [48], [49], [44], [50], [51]. Cache policies decide how to evict cache content upon cache overflows.…”

Section: Transactional Databasementioning

confidence: 99%

Competitive Consistent Caching for Transactions

Cao

Zhao

2022

2022 IEEE 38th International Conference on Data Engineering (ICDE)

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“…A MOESI protocol-used by modern AMD servers [23]-also adds the Owned state, where O encodes dirty+read-only. The potential benefit of using MOESI over MESI is the elimination of downgrade writeback traffic [85], incurred in MESI when a line in M is shared for reading with another cache. While the performance and energy difference between MOESI and MESI can be negligible [74], we discuss how MOESI's elimination of downgrade writebacks is critical in preventing a source of coherence-induced hammering in §3.2.…”

Section: Coherence Protocolsmentioning

confidence: 99%

“…One known source of coherence writes are downgrade writebacks [85], incurred in MESI-based protocols (i.e., Intel server protocols [37,53]). At a high level, the writeback occurs when a dirty line is shared with another cache, such as producer-consumer sharing [19] (repeated writer-reader).…”

Section: Source #1: Downgrade Writebacksmentioning

confidence: 99%

“…We discern that coherence-induced hammering in commodity workloads arises from three phenomena, depending on the protocol. The most basic phenomenon is that of downgrade writebacks [85], a side effect of MESI protocols, where caches must write-back dirty lines before sharing them. In ccNUMA systems-where data can be shared among caches on different nodes-these downgrade writebacks can repeatedly go to DRAM, resulting in hammering.…”

Section: Introductionmentioning

confidence: 99%

“…In ccNUMA systems-where data can be shared among caches on different nodes-these downgrade writebacks can repeatedly go to DRAM, resulting in hammering. Luckily, downgrade writebacks can be trivially eliminated by adopting widely-used MOESI protocols [85].…”

Section: Introductionmentioning

confidence: 99%

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MOESI-prime

Loughlin

Saroiu

Wolman

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Prior work shows that Rowhammer attacks-which flip bits in DRAM via frequent activations of the same row(s)-are viable. Adversaries typically mount these attacks via instruction sequences that are carefully-crafted to bypass CPU caches. However, we discover a novel form of hammering that we refer to as coherenceinduced hammering, caused by Intel's implementations of cache coherent non-uniform memory access (ccNUMA) protocols. We show that this hammering occurs in commodity benchmarks on a major cloud provider's production hardware, the first hammering found to be generated by non-malicious code. Given DRAM's rising susceptibility to bit flips, it is paramount to prevent coherenceinduced hammering to ensure reliability and security in the cloud.Accordingly, we introduce MOESI-prime, a ccNUMA coherence protocol that mitigates coherence-induced hammering while retaining Intel's state-of-the-art scalability. MOESI-prime shows that most DRAM reads and writes triggering such hammering are unnecessary. Thus, by encoding additional information in the coherence protocol, MOESI-prime can omit these reads and writes, preventing coherence-induced hammering in non-malicious and malicious workloads. Furthermore, by omitting unnecessary reads and writes, MOESI-prime has negligible effect on average performance (within ±0.61% of MESI and MOESI) and average DRAM power (0.03%-0.22% improvement) across evaluated ccNUMA configurations. CCS CONCEPTS• Security and privacy → Security in hardware; Systems security; • Hardware → Hardware reliability.

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