Our system is currently under heavy load due to increased usage. We're actively working on upgrades to improve performance. Thank you for your patience.
Optical Microlithography XXXII 2019
DOI: 10.1117/12.2524051
|View full text |Cite
|
Sign up to set email alerts
|

Full-chip application of machine learning SRAFs on DRAM case using auto pattern selection

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
7
0

Year Published

2019
2019
2023
2023

Publication Types

Select...
5
1
1

Relationship

0
7

Authors

Journals

citations
Cited by 8 publications
(8 citation statements)
references
References 4 publications
0
7
0
Order By: Relevance
“…However, today all EDA companies that offer OPC products also offer ILT products of some kind, some used for fixing hotspots like Synopsys, 19,20,98 some for model-based SRAF generation like ASML Brion. [99][100][101] ILT was extended to EUV by Synopsys [102][103][104][105] and ASML Brion started exploring using deep learning (DL) in ILT for SRAF generation. [99][100][101] Despite steady, continuing research and development across academia and industry through the decade and demonstration of the use of ILT to correct full-chip designs, ILT was still seen as an advanced method for use in critical hotspots, rather than as a technique to be applied to full-chip mask generation.…”
Section: History Of Inverse Lithographymentioning
confidence: 99%
See 2 more Smart Citations
“…However, today all EDA companies that offer OPC products also offer ILT products of some kind, some used for fixing hotspots like Synopsys, 19,20,98 some for model-based SRAF generation like ASML Brion. [99][100][101] ILT was extended to EUV by Synopsys [102][103][104][105] and ASML Brion started exploring using deep learning (DL) in ILT for SRAF generation. [99][100][101] Despite steady, continuing research and development across academia and industry through the decade and demonstration of the use of ILT to correct full-chip designs, ILT was still seen as an advanced method for use in critical hotspots, rather than as a technique to be applied to full-chip mask generation.…”
Section: History Of Inverse Lithographymentioning
confidence: 99%
“…[99][100][101] ILT was extended to EUV by Synopsys [102][103][104][105] and ASML Brion started exploring using deep learning (DL) in ILT for SRAF generation. [99][100][101] Despite steady, continuing research and development across academia and industry through the decade and demonstration of the use of ILT to correct full-chip designs, ILT was still seen as an advanced method for use in critical hotspots, rather than as a technique to be applied to full-chip mask generation. Excessive computational run-times continued to render full-chip ILT impractical in production settings.…”
Section: History Of Inverse Lithographymentioning
confidence: 99%
See 1 more Smart Citation
“…e.g., IPS sensitivity to geometry perturbation [30] (∂I max /∂M, where M is line width). Since the choice of parameter space is only engineering, alternative method is to introduce a machine learning to extract a number of parameters [31] and use them to define a parameter space. Once test patterns are identified in IPS space, any clustering algorithms can be applied for classification purpose: partitioning methods (such as K-means) or hierarchical methods (such as complete-link).…”
Section: B)mentioning
confidence: 99%
“…Shi et al proposed an optimal feature vector automatic design method based on convolution neural network (CNN), which greatly improved the computational efficiency of ILT [22] . Chen et al used Auto Pattern Selection (APS) tool to train the Newron SRAF deep learning network and successfully realized the inverse mask optimization on full-chip layout [23] . As examples, this section will detail two ILT methods based on variational autoencoder (VAE) [24] and generative adversarial network (GAN) [25] .…”
Section: Ilt Based On Standard Deep Learningmentioning
confidence: 99%