FttC-Based Fronthaul for 5G Dense/Ultra-Dense Access Network: Performance and Costs in Realistic Scenarios

Mazzenga, Franco; Giuliano, Romeo; Vatalaro, Francesco

doi:10.3390/fi9040071

Cited by 4 publications

(3 citation statements)

References 15 publications

(18 reference statements)

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“…Over recent years, FPGAs have been employed for several different applications such as the Internet of Things [21]- [23], wireless communications [24]- [25], network protocols [26]- [27], etc. The employment of FPGAs in HPC is relatively recent and still the subject of research and optimization.…”

Section: B Related Workmentioning

confidence: 99%

Design and Evaluation of a Scalable Engine for 3D-FFT Computation in an FPGA Cluster

Ammendola

Loreti

2019

Int. J. Adv. Sci. Eng. Inf. Technol.

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The Three Dimensional Fast Fourier Transform (3D-FFT) is commonly used to solve the partial differential equations describing the system evolution in several physical phenomena, such as the motion of viscous fluids described by the Navier-Stokes equations. Simulation of such problems requires the use of a parallel High-Performance Computing architecture since the size of the problem grows with the cube of the FFT size, and the representation of the single point comprises several double precision floatingpoint complex numbers. Modern High-Performance Computing (HPC) systems are considering the inclusion of FPGAs as components of this computing architecture because they can combine effective hardware acceleration capabilities and dedicated communication facilities. Furthermore, the network topology can be optimized for the specific calculation that the cluster must perform, especially in the case of algorithms limited by the data exchange delay between the processors. In this paper, we explore an HPC design that uses FPGA accelerators to compute the 3DFFT. We devise a scalable FFT engine based on a custom radix-2 doubleprecision core that is used to implement the Decimation in Frequency version of the Cooley-Tukey FFT algorithm. The FFT engine can be adapted to different technology constraints and networking topologies by adjusting the number of cores and configuration parameters in order to minimize the overall calculation time. We compare the various possible configurations with the technological limits of available hardware. Finally, we evaluate the bandwidth required for continuous FFT execution in the APEnet toroidal mesh network.

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Section: B Related Workmentioning

confidence: 99%

Design and Evaluation of a Scalable Engine for 3D-FFT Computation in an FPGA Cluster

Ammendola

Loreti

2019

Int. J. Adv. Sci. Eng. Inf. Technol.

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“…First, the access management of a large number of devices is trying to access the access point [24] - [27]. Secondly, the exploitation of licensed electromagnetic spectrum portions (already assigned to other systems) in an opportunistic way [28][29][30][31][32] nevertheless in the considered application the number of IoT sensors is limited.…”

Section: Introductionmentioning

confidence: 99%

A Feature Extractor IC for Acoustic Emission Non-destructive Testing

Giardino

Matta

Spanò

2019

Int. J. Adv. Sci. Eng. Inf. Technol.

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In this paper, we present the design and the implementation of a digital Application Specific Integrated Circuit (ASIC) for Acoustic Emission (AE) non-destructive testing. The AE non-destructive testing method is a diagnostic method used to detect faults in mechanically loaded structures and components. If a structure is subjected to mechanical load or stress, the presence of structural discontinuities releases energy in the form of acoustic emissions through the constituting material. The analysis of these acoustic emissions can be used to determine the presence of faults in several structures. The proposed circuit has been designed for IoT (Internet of Things) applications, and it can be used to simplify the existing procedures adopted for structural integrity verifications of pressurized metal tanks that, in some countries, they are based on periodic checks. The proposed ASIC is provided of Digital Signal Processing (DSP) capabilities for the extraction of the main four parameters used in the AE analysis that are the energy of the signal, the duration of the event, the number of the crossing of a certain threshold and finally the maximum value reached by the AE signal. The circuit is provided of an SPI interface capable of sending and receiving data to/from wireless transceivers to share information on the web. The DSP circuit has been coded in VHDL and synthesized in 90 nm technology using Synopsys. The circuit has been characterized in terms of area, speed, and power consumption. Experimental results show that the proposed circuit presents very low power consumption properties and low area requirements.

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“…By so doing, the user bit rate can be almost tripled, while the used physical resource is doubled. One possible use of the bonding/phantom approach is in cellular backhaul systems to feed 4G and, possibly, forthcoming 5G base stations [6]. However, once one unused copper pair (indicated in the following as ''extra pair'') is assigned to one CPE it cannot be re-used in any way to serve other CPEs even when the beneficiary CPE is not active.…”

Section: Introductionmentioning

confidence: 99%

Sharing of Copper Pairs for Improving DSL Performance in FTTx Access Networks

2019

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In this paper, we analyze two techniques allowing to significantly improve the bit rate per user in the current and future FTTx access networks. They are based on the possibility of sharing copper pairs at data link level among subscribers served by the same distributor. Sharing can be achieved by inserting low-cost devices in the current FTTx access networks. In particular, as shown in this paper, sharing of copper pairs is obtained according to two different approaches. The first approach considers the possibility of increasing bit rate by a radio-shared channel that can be accessed locally by all authorized customer premises equipments (CPEs) inside the building(s). The system providing radio access is connected to the DSLAM by means of extra and temporarily unused copper pairs in the main cable connecting the DSLAM to the distributor. The second approach considers the possibility of inserting an active transceiver device in the current passive distributor(s) bridging the DSLAM to the CPEs. Depending on the activity of CPEs connected at the same distributor, results show that both the solutions allow to achieve very high downstream bit rates per user (about 800 Mb/s at 100 m with 50% CPE activity). Devices to be inserted in the FTTx network can be realized using electronic components currently available on the market.

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FttC-Based Fronthaul for 5G Dense/Ultra-Dense Access Network: Performance and Costs in Realistic Scenarios

Cited by 4 publications

References 15 publications

Design and Evaluation of a Scalable Engine for 3D-FFT Computation in an FPGA Cluster

Design and Evaluation of a Scalable Engine for 3D-FFT Computation in an FPGA Cluster

A Feature Extractor IC for Acoustic Emission Non-destructive Testing

Sharing of Copper Pairs for Improving DSL Performance in FTTx Access Networks

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