Front-end CMOS chipset for 10 Gb/s communication

A 6 Gb/s Low Power Transimpedance Amplifier with Inductor Peaking and Gain Control for 4-channel Passive Optical Network in 0.13 μm CMOS

“…The power consumption per channel is 47.64 mW from the supply voltage of 1.2 V. The bandwidth can be enhanced with the small power consumption since the parasitic capacitances of the 1.2 V MOSFET devices are smaller than those of the 3.3 V MOSFET devices. The total gain of the TIA Core, SDC, 3-stage LA, and Output Buffer is 98.1 dBΩ, which is larger than that given in [4][5][6][7]. Also, the proposed TIA can get variable gain.…”

A 90 dBΩ, 10 Gbps Optical Receiver in a 0.18 μm CMOS Technology

“…The power dissipation is 199 mW from a single 1.8 V supply, among which 35 mW is consumed by the output buffer. Table I summarizes the performance comparison between this work, our previous work in [7], and the prior arts in [1]- [4] [13]. By a single chip integration, gain-bandwidth requirement for individual building blocks can be rearranged and further optimized.…”

“…The optical receiver provides several advantages over conventional multiple chips solutions [1]- [4]. First, tiny photo current generated from the photo detector can be on-chip enlarged to a logic level.…”

1.25-Gb/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications

“…However, silicon technologies-particularly submicron CMOS technologies-have recently become very attractive due to their low cost and high integration level characteristics. Even in terms of speed, they can provide comparable potential to GaAs technologies [1].…”