From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus

Lin, Dian-Lun; Ren, Haoxing; Zhang, Yanqing; Khailany, Brucek; Huang, Tsung‐Wei

doi:10.1145/3545008.3545091

Cited by 16 publications

(2 citation statements)

References 6 publications

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“…The result is that it is currently infeasible to evaluate the performance of large workloads on the RTL level. Recent works [27]- [29] addressed the problem of accelerating RTL simulation by leveraging techniques like batch processing, task-level dataflow execution, low-level parallelism, selective execution, etc. These orthogonal techniques to speed up simulation may not scale well for very large workloads.…”

Section: E the Quest For Advanced And Efficient Samplingmentioning

confidence: 99%

Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation

Sabu,

Liu,

Carlson

2024

IEEE Access

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Pre-silicon performance evaluation is a crucial component of computer systems research and development. While simulation has long been the de facto standard in this context, it can be prohibitively time-consuming for long-running, realistic workloads. To expedite this process, researchers have traditionally turned to sampling techniques. However, these techniques typically rely on fixed-length intervals for analysis, which can often be out of sync with the periodicity of program execution. Additionally, since an application's phase behavior is strongly correlated to the code it executes, it can exhibit a hierarchy of phase behaviors that can be observed at various interval lengths, rendering conventional sampling techniques inadequate. To address these limitations, we propose Viper -a novel sampled simulation methodology that applies to single-threaded and multi-threaded workloads by leveraging the hierarchical structure of program execution. Viper takes into account both application periodicity and inter-thread synchronization in order to achieve better sampling accuracy and smaller regions, which enables faster register-transfer level (RTL) simulations. We evaluate Viper with the multi-threaded SPEC CPU2017 benchmarks and demonstrate a significant simulation speedup (up to 2,710×, 358× on average for the train input set) while maintaining an average sampling error of just 1.32%.

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Section: E the Quest For Advanced And Efficient Samplingmentioning

confidence: 99%

Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation

Sabu,

Liu,

Carlson

2024

IEEE Access

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“…RTFlow [21] is a GPU-accelerated RTL simulator that exploits stimulus-level parallelism to speed up simulation by running many independent simulations on a GPU. RTLFlow improves execution speed by up to 40× over Verilator for many stimuli, but it runs an order magnitude slower than Verilator with a single stimulus.…”

Section: Parallel Rtl Simulationmentioning

confidence: 99%

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

Emami¹,

Kashani²,

Kamahori³

et al. 2023

Preprint

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The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware heavily uses cycle-accurate simulation of register-transfer-level (RTL) designs. The best software RTL simulators can simulate designs at 1-1000 kHz, i.e., more than three orders of magnitude slower than hardware. Faster simulation can increase productivity by speeding design iterations and permitting more exhaustive exploration.One possibility is to use parallelism as RTL exposes considerable fine-grain concurrency. However, state-of-the-art RTL simulators generally perform best when single-threaded since modern processors cannot effectively exploit fine-grain parallelism.This work presents Manticore: a parallel computer designed to accelerate RTL simulation. Manticore uses a static bulk-synchronous parallel (BSP) execution model to eliminate runtime synchronization barriers among many simple processors. Manticore relies entirely on its compiler to schedule resources and communication. Because RTL code is practically free of long divergent execution paths, static scheduling is feasible. Communication and synchronization no longer incur runtime overhead, enabling efficient fine-grain parallelism. Moreover, static scheduling dramatically simplifies the physical implementation, significantly increasing the potential parallelism on a chip. Our 225-core FPGA prototype running at 475 MHz outperforms a state-of-the-art RTL simulator on an Intel Xeon processor running at ≈ 3.3 GHz by up to 27.9× (geomean 5.3×) in nine Verilog benchmarks.

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TaroRTL: Accelerating RTL Simulation Using Coroutine-Based Heterogeneous Task Graph Scheduling

Lin,

Ogras,

Miguel

et al. 2024

Lecture Notes in Computer Science

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From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus

Cited by 16 publications

References 6 publications

Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation

Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core Simulation

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

TaroRTL: Accelerating RTL Simulation Using Coroutine-Based Heterogeneous Task Graph Scheduling

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