From LIF to AdEx neuron models: Accelerated analog 65 nm CMOS implementation

Aamir, Syed Ahmed; Müller, Paul; Kriener, Laura; Kiene, Gerd; Schemmel, Johannes; Meier, K.

doi:10.1109/biocas.2017.8325167

Cited by 5 publications

(4 citation statements)

References 23 publications

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“…In each column, the current pulses of excitatory and inhibitory synapses are summed up and low-pass-filtered by two corresponding inputs in the neuron circuits [1]. In both BrainScaleS generations these implement the adaptive exponential leaky integrate-and-fire model [25]…”

Section: Neuron Circuitsmentioning

confidence: 99%

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Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System

Grübl

Billaudelle

Cramer

et al. 2020

J Sign Process Syst

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This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.

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Section: Neuron Circuitsmentioning

confidence: 99%

“…Neuron circuits Synaptic currents are forwarded to the neuron circuits [1]. In both BrainScaleS generations they implement the adaptive exponential leaky integrate-andfire model [22]…”

Section: Synapse Arraymentioning

confidence: 99%

Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System

Grübl

Billaudelle

Cramer

et al. 2020

J Sign Process Syst

Self Cite

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“…Furthermore, it was shown to feature multicompartmental neuron design, supporting the morphologically detailed realization of neural networks ( Yang et al, 2019 ). Biologically plausible spiking neurons were also implemented in analog circuits, featuring spike adaptation ( Aamir et al, 2017 ). Although incredibly versatile and highly configurable, these designs were guided by a bottom–up approach, tailored to reproduce biological behavior.…”

Section: Discussionmentioning

confidence: 99%

Neuromorphic Analog Implementation of Neural Engineering Framework-Inspired Spiking Neuron for High-Dimensional Representation

Hazan

Tsur

2021

Front. Neurosci.

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Brain-inspired hardware designs realize neural principles in electronics to provide high-performing, energy-efficient frameworks for artificial intelligence. The Neural Engineering Framework (NEF) brings forth a theoretical framework for representing high-dimensional mathematical constructs with spiking neurons to implement functional large-scale neural networks. Here, we present OZ, a programable analog implementation of NEF-inspired spiking neurons. OZ neurons can be dynamically programmed to feature varying high-dimensional response curves with positive and negative encoders for a neuromorphic distributed representation of normalized input data. Our hardware design demonstrates full correspondence with NEF across firing rates, encoding vectors, and intercepts. OZ neurons can be independently configured in real-time to allow efficient spanning of a representation space, thus using fewer neurons and therefore less power for neuromorphic data representation.

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“…One particular example is the BrainScaleS system, which represents a combination of von Neumann and mixed-signal neuromorphic computing principles. Compared to the biological model archetype, the BrainScaleS implementation operates in accelerated time: characteristic model time constants are reduced by a factor of 10 3 −10 4 (Aamir et al, 2017 ; Schmitt et al, 2017 ). In addition, an embedded processor provides more flexibility, especially with respect to programmable plasticity (Friedmann et al, 2017 ).…”

Section: Hardware and Software Platformsmentioning

confidence: 99%

Code Generation in Computational Neuroscience: A Review of Tools and Techniques

Blundell

Brette

Cleland

et al. 2018

Front. Neuroinform.

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Advances in experimental techniques and computational power allowing researchers to gather anatomical and electrophysiological data at unprecedented levels of detail have fostered the development of increasingly complex models in computational neuroscience. Large-scale, biophysically detailed cell models pose a particular set of computational challenges, and this has led to the development of a number of domain-specific simulators. At the other level of detail, the ever growing variety of point neuron models increases the implementation barrier even for those based on the relatively simple integrate-and-fire neuron model. Independently of the model complexity, all modeling methods crucially depend on an efficient and accurate transformation of mathematical model descriptions into efficiently executable code. Neuroscientists usually publish model descriptions in terms of the mathematical equations underlying them. However, actually simulating them requires they be translated into code. This can cause problems because errors may be introduced if this process is carried out by hand, and code written by neuroscientists may not be very computationally efficient. Furthermore, the translated code might be generated for different hardware platforms, operating system variants or even written in different languages and thus cannot easily be combined or even compared. Two main approaches to addressing this issues have been followed. The first is to limit users to a fixed set of optimized models, which limits flexibility. The second is to allow model definitions in a high level interpreted language, although this may limit performance. Recently, a third approach has become increasingly popular: using code generation to automatically translate high level descriptions into efficient low level code to combine the best of previous approaches. This approach also greatly enriches efforts to standardize simulator-independent model description languages. In the past few years, a number of code generation pipelines have been developed in the computational neuroscience community, which differ considerably in aim, scope and functionality. This article provides an overview of existing pipelines currently used within the community and contrasts their capabilities and the technologies and concepts behind them.

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From LIF to AdEx neuron models: Accelerated analog 65 nm CMOS implementation

Cited by 5 publications

References 23 publications

Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System

Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System

Neuromorphic Analog Implementation of Neural Engineering Framework-Inspired Spiking Neuron for High-Dimensional Representation

Code Generation in Computational Neuroscience: A Review of Tools and Techniques

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