From Design to System-Technology optimization for CMOS

Ryckaert, Julien; Chehab, Bilal; Jang, Doyoung; Mirabelli, G.; Salahuddin, Shairfe Muhammad; Schuddinck, P.; Zografos, Odysseas; Zubair, A.; Weckx, Pieter; Hellings, Geert

doi:10.1109/vlsi-tsa51926.2021.9440115

Cited by 12 publications

(8 citation statements)

References 6 publications

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“…The FET1-series contains one NW, one NS and one FS FET. The NW diameter is typical for fabricated NW FETs [32], while the NS and FS width W and height H are based on the imec roadmap [33] and are considered typical for a 2 nm technology node. The reduced pto-n separation of the FS allows one to make it wider compared to the NS (W (FS) = 21 nm vs. W (NS) = 14.5 nm).…”

Section: A Device Structuresmentioning

confidence: 99%

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs

Vandemaele

Kaczer

Tyaginov

et al. 2022

2022 IEEE International Reliability Physics Symposium (IRPS)

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Forksheet (FS) FETs are a novel transistor architecture consisting of vertically stacked nFET and pFET sheets at opposite sides of a dielectric wall. The wall allows reducing the p-to nFET separation (p-to-n separation), thus enabling further logic cell area scaling without requiring gate length scaling. We report hot-carrier degradation (HCD) simulations of FS FETs and compare this architecture to nanowire (NW) and nanosheet (NS) FETs. HCD is shown to decrease with increasing sheet width in both NS and FS FETs when taking interface state generation into account. Considering that a FS FET can be made wider than an NS FET because of the reduced p-to-n separation, lower HCD for the FS FET is observed. Finally, we make an initial assessment of the impact of oxide defect charging in the FS wall. We confirm decreasing influence of fixed wall charge for increasing sheet widths and estimate that the overall impact of wall charging will stay under control at operating conditions.

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Section: A Device Structuresmentioning

confidence: 99%

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs

Vandemaele

Kaczer

Tyaginov

et al. 2022

2022 IEEE International Reliability Physics Symposium (IRPS)

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“…Without a proper dimensional scaling, considering the higher complexity, the cost of each future technology is set to increase. Therefore, we analyze the cost scaling to the A10/7 node, considering the Vertical-Horizontal-Vertical (VHV) architecture and the Complementary-FET (CFET), along with scaling boosters [2,3].…”

Section: Introductionmentioning

confidence: 99%

Cost analysis of device options and scaling boosters below the A14 technology node

Mirabelli

Vandooren

Neve

et al. 2023

DTCO and Computational Patterning II

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The saturation in dimensional scaling has clearly impacted the semiconductor technology roadmap. The extension of patterning cliffs through new tools and multi-patterning lithography, as well as the introduction of innovative scaling boosters is helping in optimally scaling the Power-Performance-Area (PPA) metrics. However, because of the increase in the process complexity and reduced area benefits, manufacturing cost is increasing. Therefore, moving to a PPA-Cost (PPAC) methodology to monitor and analyze the cost of a technology is becoming increasingly necessary.

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“…Nonetheless, other challenges remain. [10][11][12][13] In fact, whereas in a 5T SDC a classical horizontal-vertical-horizontal (HVH) routing approach could still be implemented, beyond that (i.e. for 4T SDC), such a scheme would leave a very small accessibility window for input and output pins, as visible in Fig.…”

Section: Introductionmentioning

confidence: 99%

Resistance modeling of short-range connections: impact of current spreading

Tierno

Vega-Gonzalez

Esposto

et al. 2023

Jpn. J. Appl. Phys.

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We investigated the impact of current spreading on the resistance of short-range connections by performing simulations in Synopsys Sentaurus, based on a calibrated resistivity model. As a main case study, we considered vertical-horizontal-vertical (VHV) connections, a novel cell-routing architecture based on a two-level middle-of-line scheme, that has been proposed to boost the routing of four-track standard cells beyond the 2 nm technology node. We analyzed the impact of vias and line geometry on VHV link resistance and we found that low aspect ratio (AR) lines are needed to minimize the average cell resistance. We performed extensive resistance simulations of various short-range connection schemes beyond VHV links. We concluded that large AR lines are detrimental in all cases in which the link resistance is dominated by the vias. Finally, we show that ignoring current spreading can lead to a significant miscalculation of the link resistance in such scenarios.

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From Design to System-Technology optimization for CMOS

Cited by 12 publications

References 6 publications

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs

Cost analysis of device options and scaling boosters below the A14 technology node

Resistance modeling of short-range connections: impact of current spreading

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