Cost analysis of device options and scaling boosters below the A14 technology node

Abstract

The saturation in dimensional scaling has clearly impacted the semiconductor technology roadmap. The extension of patterning cliffs through new tools and multi-patterning lithography, as well as the introduction of innovative scaling boosters is helping in optimally scaling the Power-Performance-Area (PPA) metrics. However, because of the increase in the process complexity and reduced area benefits, manufacturing cost is increasing. Therefore, moving to a PPA-Cost (PPAC) methodology to monitor and analyze the cost of a technology is becoming increasingly necessary.

Investigation of die-cost scaling scenarios in future technologies

“…The steady increase in manufacturing cost is related to multi-patterning schemes, scaling boosters and novel device architectures in FEOL and MOL. [2] In addition, not only the BEOL requires tight metal pitches, but the number of metal layers steadily increases in novel technologies due to the higher requirements of routing resources.…”