Frequency Synthesizer With Dual Loop Frequency and Gain Calibration

Jakobsson, Anders; Grewing, Christian; Serban, Adriana; Gong, Shaofang

doi:10.1109/tcsi.2013.2256191

Cited by 10 publications

(3 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Praleidžiamų dažnių ruožo pločiui padidinti ir dažnio suderinimo trukmei sumažinti, stengiantis neįtakoti sintezatoriaus fazinio triukšmo, yra naudojamos I-ojo tipo fazės derinimo kilpos (Hedayati, Bakkaloglu 2012;Shekhar et al 2011), vienpoliai fazės detektoriai, dvigubos kilpos struktūros (Cai et al 2013;Chen X., Chen Y. 2011;Cowan, Williams 2013;Jakobsson et al 2013) arba kvarcinį generatorių pakeičianti antroji FDK (Shekhar et al 2011).…”

Section: įVadasunclassified

Analysis of Frequency Synthesisers for Multistandart Wireless Transceiver / Dažnio Sintezatorių Daugiastandarčiams Bevielio Ryšio Siųstuvams Ir Imtuvams Analizė

Jurgo

Navickas

2016

Mokslas – Lietuvos Ateitis

View full text Add to dashboard Cite

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

show abstract

Section: įVadasunclassified

Analysis of Frequency Synthesisers for Multistandart Wireless Transceiver / Dažnio Sintezatorių Daugiastandarčiams Bevielio Ryšio Siųstuvams Ir Imtuvams Analizė

Jurgo

Navickas

2016

Mokslas – Lietuvos Ateitis

View full text Add to dashboard Cite

show abstract

“…When the input event occurs, the integration is performed up to the current simulation time . This is done using the previous input value/slope, according to (5) with the corresponding code shown in line 34-38. To find the time advance , a change of variables is performed, i.e., .…”

Section: B External Transition Handlingmentioning

confidence: 99%

“…However, there are still drawbacks to using a SPICE-type analog solver, as illustrated in the case of a 0. 18 CMOS, 3.5-GHz phase-locked loop (PLL) with dual loop frequency and gain calibration [5], shown in Fig. 1.…”

mentioning

confidence: 99%

Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS

Jakobsson

Serban

Gong

2015

IEEE Trans. Circuits Syst. I

Self Cite

View full text Add to dashboard Cite

A method to implement quantized-state system (QSS) models in industry standard RF-IC design tools is proposed. The method is used to model a GHz-range 0.18 CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First-and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first described in detail. These models do not rely on analog nets, and use only the event-based solver. Then, simulation results are compared to reference SPICE simulation results to prove the validity of the QSS method. The entire PLL circuit is finally simulated using the QSS model of the loop-filter, charge-pump and VCO, in conjunction with standard high-level models of the PLL digital circuits. To verify the proposed QSS method, measured phase noise is compared with simulated phase noise. It is shown that simulated phase noise accurately predicts the measured phase noise with improved accuracy, and an increase in simulation efficiency by more than 50 times. Measured and simulated results generally demonstrate the feasibility of the QSS modeling for mixed-signal circuit simulation and design.

show abstract

Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application

Pradhan

Jana

2022

Circuits Syst Signal Process

View full text Add to dashboard Cite

Frequency Synthesizer With Dual Loop Frequency and Gain Calibration

Cited by 10 publications

References 10 publications

Analysis of Frequency Synthesisers for Multistandart Wireless Transceiver / Dažnio Sintezatorių Daugiastandarčiams Bevielio Ryšio Siųstuvams Ir Imtuvams Analizė

Analysis of Frequency Synthesisers for Multistandart Wireless Transceiver / Dažnio Sintezatorių Daugiastandarčiams Bevielio Ryšio Siųstuvams Ir Imtuvams Analizė

Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS

Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application

Contact Info

Product

Resources

About