FreewayNoC: A DDR NoC with Pipeline Bypassing

Ejaz, Ahsen; Papaefstathiou, Vassilios; Sourdis, Ioannis

doi:10.1109/nocs.2018.8512160

Cited by 14 publications

(18 citation statements)

References 19 publications

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“…The analysis shows that higher capacitance and low series resistance lowers the voltage drop. A design of freeway Network On-Chip (NoC) is proposed in [12] which routes flits on DDR and allows bypass pipelining. Pipeline bypassing reduces the packet latency at a low traffic load.…”

Section: Literature Reviewmentioning

confidence: 99%

PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories

Fadnavis¹,

B.S²

2021

IJATEE

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The large-scale growth of the electronics industry in the past decade has led to small-sized gadgets flooding the market. Initially, only Personal Computers (PC) employed the use of multi-core processing, however, now even small hand-held gadgets have come to possess similar computational power as the PC and laptop. With mobile manufacturers opting for multicore processing and graphics -intensive application usage, memory storage and access has become a crucial aspect to achieve high performance.

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Section: Literature Reviewmentioning

confidence: 99%

PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories

Fadnavis¹,

B.S²

2021

IJATEE

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“…No recent publications about NoCs that are particularly aimed for MCPs have been found. For NoCs accommodated to CISCs, there are recent publications, such as FastTrackNoC [23] and FreewayNoC [24] which are compared to several state-of-the-art NoCs and found to be superior. Their area and energy consumption are much higher than those of the Bubble NoC, while the speeds are in the same order.…”

Section: B Detailed Comparisonmentioning

confidence: 99%

“…State-of-the-art for 14 nm VLSI technology is air-isolated wires with a capacitance of 0.15 fF/μm and a resistance of 2.7 Ω/μm [25], thereby providing a time constant of 0.405 fs/μm². The delay for the 150 μm wire in a Bubble NoC is 9.1 ps and applied to FastTrackNoC with 2.1 mm [23] wires it is 1.8 ns, and for FreewayNoC with 2.85 mm [24] wires it is 3.3 ns according to Spice. Some kind of sense amplifier is required to exceed the time constant.…”

Section: ) Wire Delaysmentioning

confidence: 99%

Bubble NoC – A Low Energy Network-on-Chip with Small Footprint and High Performance

Carlstedt¹,

Rimborg²

2021

Preprint

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<div>The Bubble NoC is based on simplicity and provides outstanding performance. Flow control is implemented by <i>bubbles</i>, which are inserted between the flits. The logic resembles a traffic situation where a vehicle only moves if the next position is empty. When a flit moves, a bubble is created behind it, and when there is a blocking the bubbles are collapsed as the flits behind are packed together. Even when the Bubble NoC is saturated, it degrades gracefully, and the execution continues.</div><div> Deterministic prerouting is used, with the address stored as markers in a 2 out of 32 code. The routing algorithm shifts the address one step at each hop and turns or finishes when a marker starts the address.</div><div> The physical implementation is a mesh of <i>streets</i> containing duplex links of 38 wires carrying 32-bit payload. Signaling is based on current injection that charges the wires. A switch is placed in a four-way crossing, with a fifth local connection into a street. The switch contains input registers for each approaching street. Straight through traffic is simply passed on, and a diagonal gate is used for turning traffic.</div><div> All switches are bidirectional transmission gates, and the control is distributed as a sidewalk in a few µm of the periphery surrounding the intersection. In a 14 nm technology, the streets are 8 μm wide, the crossing is 17 μm in square, the hop frequency 6.67 GHz and the energy for a datapath 4.1 fJ/bit/hop (150 µm).</div>

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“…On the other hand, there are many existing works focusing on shortening the latency of routers [9,12,13,16,[20][21][22]. Additionally, Kumar et al proposed express channels which enable multi-hop packets to bypass intermediate routers [16].…”

Section: Related Workmentioning

confidence: 99%

“…Thirdly, routing at each hop and buffer allocations/accesses deepen the router pipelines and further increase the latency. To tackle these concerns, many optimization techniques are proposed [2,5,7,9,11,13,[19][20][21][22]. Despite the effectiveness of such techniques directly addressing power and performance issues, there are also attempts that question the necessity of VC flow control, buffering and arbitrations in modern NoCs.…”

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confidence: 99%

Energy-Efficient On-Chip Networks through Profiled Hybrid Switching

Jiao

Cao³

et al. 2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

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Virtual channel (VC) flow control is the de facto choice for modern networks-on-chip (NoCs) to allow better utilization of the link bandwidth through buffering and packet switching (PS), which are also the sources of large power footprint and long per-hop latency. However, bandwidth can be plentiful for parallel workloads under VC flow control. Thus, dated but simpler mechanisms, such as circuit switching (CS), can help improve the energy efficiency of modern NoCs. In this paper, we propose to apply CS to part of the link bandwidth so that a considerable amount of traffic can be transmitted bufferlessly without routing. Evaluations reveal that this proposal leads to a reduction of energy per flit by up to 32% while also provides very competitive latency when compared to networks under VC flow control. CCS CONCEPTS • Networks → Network on chip; • Computer systems organization → Interconnection architectures; Multicore architectures.

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FreewayNoC: A DDR NoC with Pipeline Bypassing

Cited by 14 publications

References 19 publications

PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories

PNR flow methodology for congestion optimization using different macro placement strategies of DDR memories

Bubble NoC – A Low Energy Network-on-Chip with Small Footprint and High Performance

Energy-Efficient On-Chip Networks through Profiled Hybrid Switching

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