Fractal Coherence: Scalably Verifiable Cache Coherence

Zhang, Meng; Lebeck, Alvin R.; Sorin, Daniel J.

doi:10.1109/micro.2010.11

Cited by 51 publications

(48 citation statements)

References 33 publications

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“…To facilitate verification of cache coherence, the nonscalable verification step from Section 2.1, we leverage Fractal Coherence [10]. Fractal Coherence is a design methodology for cache coherence protocols that can be formally verified using existing, automated, easy-to-use formal verification tools.…”

Section: Fractal Coherencementioning

confidence: 99%

“…Verification Process: As proven in the original Fractal Coherence paper [10], Fractal Coherence protocols can be formally verified to maintain cache coherence for any number of cores, using two scalable verification steps. First, we must verify that the minimum system is coherent Second, we must verify the fractal behavior, i.e., the larger-scale systems behave like the minimum system.…”

Section: Cache Coherencementioning

confidence: 99%

“…Fractal Coherence [10] presents a design methodology for verifiable cache coherence, but coherence is not sufficient. Consistency defines architectural correctness, whereas coherence is a microarchitectural mechanism that helps to support consistency.…”

Section: Introductionmentioning

confidence: 99%

“…1 Of those three verification steps, two are simple and scalable, but the third step is not. To make that step simpler and scalable, we use the result of the other relevant prior work: Fractal Coherence [10]. We now discuss the relevant aspects of both DVMC (Section 2.1) and Fractal Coherence (Section 2.2).…”

Section: Introductionmentioning

confidence: 99%

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Fractal Consistency: Architecting the Memory System to Facilitate Verification

Zhang

Lebeck

Sorin

2010

IEEE Comput. Arch. Lett.

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Abstract-One of the most challenging problems in developing a multicore processor is verfiying that the design is correct, and one of the most difficult aspects of pre-silicon verification is verifying that the memory system obeys the architecture's specified memory consistency model. To simplify the process of pre-silicon design verification, we propose a system model called the Fractally Consistent Model (FCM). We prove that systems that adhere to the FCM can be verified to obey the memory consistency model in three simple, scalable steps. The procedure for verifying FCM systems contrasts sharply with the difficult, non-scalable procedure required to verify non-FCM systems. We show that FCM systems do not necessarily sacrifice performance, compared to non-FCM systems, despite being simpler to verify.

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Section: Fractal Coherencementioning

confidence: 99%

Section: Cache Coherencementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Fractal Consistency: Architecting the Memory System to Facilitate Verification

Zhang

Lebeck

Sorin

2010

IEEE Comput. Arch. Lett.

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“…The design of even a simple coherence protocol is not trivial; under a coherence protocol, the response to a given request is determined by the state of all actors in the system, transient states due to indirections (e.g., cache line invalidation), and transient states due to the nondeterminism inherent in the relative timing of events. Since the state space explodes exponentially as the distributed directories and the number of cores grow, it is virtually impossible to cover all scenarios during verification either by simulation or by formal methods [18]. Unfortunately, verifying small subsystems does not guarantee the correctness of the entire system [3].…”

Section: Introductionmentioning

confidence: 99%

The Execution Migration Machine: Directoryless Shared-Memory Architecture

et al. 2015

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Distributed directory cache coherence protocols for current many-core CMPs are not only difficult and error-prone to implement and verify, but also provide suboptimal performance when a thread requires access to large amounts of data distributed across the chip: the data must be brought to the core where the thread is running, incurring delays and energy costs. In this paper, we propose an approach based on the combination of partial-context thread migration and a directory-free remote access protocol: for these kinds of applications, our architecture can outperform directory-based cache coherence. In addition, unlike with distributed cache coherence protocols, the verification complexity of our architecture does not grow with the number of cores.

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Rainbow: A composable coherence protocol for multi‐chip servers

Menezo

Puente

Gregorio

2020

Concurrency and Computation

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The use of multi-chip modules (MCM) and/or multi-socket boards is the most suitable approach to increase the computation density of servers while keep chip yield attained. This article introduces a new coherence protocol suitable, in terms of complexity and scalability, for this class of systems. The proposal uses two complementary ideas: (1) A mechanism that dissociates complexity from performance by means of colored-token counting, (2) A construct that optimizes performance and cost by means of two functionally symmetrical structures working in the last level cache of each chip and each memory controller. The coordinated work of both structures minimizes the coherence-related effects on the average memory latency perceived by the processor. Our proposal is able to improve on the performance of a HyperTransport-like coherence protocol by from 25% to 60%.

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Fractal Coherence: Scalably Verifiable Cache Coherence

Abstract: Abstract

Cited by 51 publications

References 33 publications

Fractal Consistency: Architecting the Memory System to Facilitate Verification

Fractal Consistency: Architecting the Memory System to Facilitate Verification

The Execution Migration Machine: Directoryless Shared-Memory Architecture

Rainbow: A composable coherence protocol for multi‐chip servers

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