FPGA Verification of a Single QC-LDPC Code for 100 Gb/s Optical Systems without Error Floor down to BER of 10−15

Chang, Deyuan; Yu, Fan; Xiao, Zijian; Li, Yang; Stojanović, Nebojša; Xie, Changsong; Shi, Xiaozhong; Xu, Xiaogeng; Xiong, Qianjin

doi:10.1364/ofc.2011.otun2

Cited by 83 publications

(40 citation statements)

References 3 publications

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“…At room temperature, the measured EVM m is 14.7% and the measured BER amounts to 4.3 × 10 −3 , just below the threshold for hard-decision FEC. For operation at 80 °C, the EVM m is measured to be 17.6%, and the measured BER is 1.3 × 10 −2 , still below the threshold of 2.4 × 10 −2 for soft-decision FEC with 20% overhead [31]. At room temperature, the line rate (net data rate) of the 64 GBd 4ASK signal amounts to 128 Gbit/s (120 Gbit/s).…”

Section: Measurementsmentioning

confidence: 96%

Generation of 64 GBd 4ASK signals using a silicon-organic hybrid modulator at 80°C

et al. 2016

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Abstract:We demonstrate a silicon-organic hybrid (SOH) Mach-Zehnder modulator (MZM) generating four-level amplitude shift keying (4ASK) signals at symbol rates of up to 64 GBd both at room temperature and at an elevated temperature of 80 °C. The measured line rate of 128 Gbit/s corresponds to the highest value demonstrated for silicon-based MZM so far. We report bit error ratios of 10 −10 (64 GBd BPSK), 10 −5 (36 GBd 4ASK), and 4 × 10 −3 (64 GBd 4ASK) at room temperature. At 80 °C, the respective bit error ratios are 10 −10 , 10 −4 , and 1.3 × 10 −2 . The hightemperature experiments were performed in regular oxygen-rich ambient atmosphere. ©2016 Optical Society of America

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Section: Measurementsmentioning

confidence: 96%

Generation of 64 GBd 4ASK signals using a silicon-organic hybrid modulator at 80°C

et al. 2016

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“…The FEC operating in large Galois field (GF) that matches the size of multilevel modulation formats, called the non-binary FEC coded modulation, which deals with modulation symbol directly was reported in [3]. Due to the extensively computation complexity of the nonbinary CM, the binary FEC together with a soft de-mapper that maps symbol to bit is widely adopted both in simulation and experimental demonstrations, and it has been shown that capacity approaching performance are possible even with binary CM [4,5]. On the other hand, the non-uniform probabilistic shaping over conventional square quadrature amplitude modulation (QAM), which theoretically can come closer to the Shannon limit, have been extensively studied recently [7,8].…”

Section: Introductionmentioning

confidence: 99%

FPGA-based LDPC-coded APSK for optical communication systems

2017

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Abstract:In this paper, with the aid of mutual information and generalized mutual information (GMI) capacity analyses, it is shown that the geometrically shaped APSK that mimics an optimal Gaussian distribution with equiprobable signaling together with the corresponding gray-mapping rules can approach the Shannon limit closer than conventional quadrature amplitude modulation (QAM) at certain range of FEC overhead for both 16-APSK and 64-APSK. The field programmable gate array (FPGA) based LDPC-coded APSK emulation is conducted on block interleaver-based and bit interleaver-based systems; the results verify a significant improvement in hardware efficient bit interleaver-based systems. In bit interleaver-based emulation, the LDPC-coded 64-APSK outperforms 64-QAM, in terms of symbol signal-to-noise ratio (SNR), by 0.1 dB, 0.2 dB, and 0.3 dB at spectral efficiencies of 4.8, 4.5, and 4.2 b/s/Hz, respectively. It is found by emulation that LDPC-coded 64-APSK for spectral efficiencies of 4.8, 4.5, and 4.2 b/s/Hz is 1.6 dB, 1.7 dB, and 2.2 dB away from the GMI capacity.

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“…With the advance of analog-to-digital converter technologies, high order modulation formats up to 64-QAM with symbol rate up to 72-Gbaud has been demonstrated experimentally with Raman amplification [3]. To accommodate such high-speed optical communication system, the high-performing FEC engines that can support throughputs of 400-Gbit/s or multiple thereof are needed, which have low power consumption, providing high net coding gains at a target bit error rate of 10 −15 , and that are preferably adaptable to the time-varying optical channel conditions [4,5]. Recently, soft-decision binary and non-binary LDPC codes with an outer hard-decision code pushing the system BER to levels below target BER have been proposed in [6,7].…”

Section: Introductionmentioning

confidence: 99%

FPGA-based rate-adaptive LDPC-coded modulation for the next generation of optical communication systems

Zou

Djordjević

2016

Opt. Express

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Abstract:In this paper, we propose a rate-adaptive FEC scheme based on LDPC codes together with its software reconfigurable unified FPGA architecture. By FPGA emulation, we demonstrate that the proposed class of rate-adaptive LDPC codes based on shortening with an overhead from 25% to 42.9% provides a coding gain ranging from 13.08 dB to 14.28 dB at a post-FEC BER of 10 −15 for BPSK transmission. In addition, the proposed rate-adaptive LDPC coding combined with higher-order modulations have been demonstrated including QPSK, 8-QAM, 16-QAM, 32-QAM, and 64-QAM, which covers a wide range of signal-to-noise ratios. Furthermore, we apply the unequal error protection by employing different LDPC codes on different bits in 16-QAM and 64-QAM, which results in additional 0.5dB gain compared to conventional LDPC coded modulation with the same code rate of corresponding LDPC code.

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FPGA Verification of a Single QC-LDPC Code for 100 Gb/s Optical Systems without Error Floor down to BER of 10−15

Cited by 83 publications

References 3 publications

Generation of 64 GBd 4ASK signals using a silicon-organic hybrid modulator at 80°C

Generation of 64 GBd 4ASK signals using a silicon-organic hybrid modulator at 80°C

FPGA-based LDPC-coded APSK for optical communication systems

FPGA-based rate-adaptive LDPC-coded modulation for the next generation of optical communication systems

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