FPGA simulation engine for customized construction of neural microcircuits

Blair, Hugh T.; Cong, Jason; Wu, Di

doi:10.1109/iccad.2013.6691179

Cited by 4 publications

(3 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Hardware support for neural networks. There is an extensive body of work on hardware implementation of neural networks both in digital [38], [19], [58], [12], [16], [7] and analog [8], [45], [49], [32] domains. Other work has examined fault-tolerant hardware neural networks [29], [50].…”

Section: Related Workmentioning

confidence: 99%

SNNAP: Approximate computing on programmable SoCs via neural acceleration

Moreau

Wyse

Nelson

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

View full text Add to dashboard Cite

Many applications that can take advantage of accelerators are amenable to approximate execution. Past work has shown that neural acceleration is a viable way to accelerate approximate code. In light of the growing availability of on-chip field-programmable gate arrays (FPGAs), this paper explores neural acceleration on off-the-shelf programmable SoCs.We describe the design and implementation of SNNAP, a flexible FPGA-based neural accelerator for approximate programs. SNNAP is designed to work with a compiler workflow that configures the neural network's topology and weights instead of the programmable logic of the FPGA itself. This approach enables effective use of neural acceleration in commercially available devices and accelerates different applications without costly FPGA reconfigurations. No hardware expertise is required to accelerate software with SNNAP, so the effort required can be substantially lower than custom hardware design for an FPGA fabric and possibly even lower than current "C-to-gates" highlevel synthesis (HLS) tools. Our measurements on a Xilinx Zynq FPGA show that SNNAP yields a geometric mean of 3.8× speedup (as high as 38.1×) and 2.8× energy savings (as high as 28×) with less than 10% quality loss across all applications but one. We also compare SNNAP with designs generated by commercial HLS tools and show that SNNAP has similar performance overall, with better resource-normalized throughput on 4 out of 7 benchmarks.

show abstract

Section: Related Workmentioning

confidence: 99%

SNNAP: Approximate computing on programmable SoCs via neural acceleration

Moreau

Wyse

Nelson

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

View full text Add to dashboard Cite

show abstract

“…Here, we modify the original circuit, so that the activity bump circulates in only one direction. The model was implemented using an engine for simulating integrate-and-fire networks in real time on field-programmable gate array (FPGA) microchips [ 54 ] (see electronic supplementary material, Methods).…”

Section: A Ring Attractor Network For Synchronization Codingmentioning

confidence: 99%

Oscillatory neurocomputing with ring attractors: a network architecture for mapping locations in space onto patterns of neural synchrony

Blair¹,

Wu²,

Cong³

2014

Phil. Trans. R. Soc. B

Self Cite

View full text Add to dashboard Cite

Theories of neural coding seek to explain how states of the world are mapped onto states of the brain. Here, we compare how an animal's location in space can be encoded by two different kinds of brain states: population vectors stored by patterns of neural firing rates, versus synchronization vectors stored by patterns of synchrony among neural oscillators. It has previously been shown that a population code stored by spatially tuned ‘grid cells’ can exhibit desirable properties such as high storage capacity and strong fault tolerance; here it is shown that similar properties are attainable with a synchronization code stored by rhythmically bursting ‘theta cells’ that lack spatial tuning. Simulations of a ring attractor network composed from theta cells suggest how a synchronization code might be implemented using fewer neurons and synapses than a population code with similar storage capacity. It is conjectured that reciprocal connections between grid and theta cells might control phase noise to correct two kinds of errors that can arise in the code: path integration and teleportation errors. Based upon these analyses, it is proposed that a primary function of spatially tuned neurons might be to couple the phases of neural oscillators in a manner that allows them to encode spatial locations as patterns of neural synchrony.

show abstract

“…FPGAs have previously been used as an accelerator for neural simulation, both for conductance-based models (Graas et al, 2004 ; Blair et al, 2013 ; Smaragdos et al, 2014 ) and for point-neurons (Cassidy et al, 2007 ; Cheung et al, 2009 ; Rice et al, 2009 ; Thomas and Luk, 2009 ; Moore et al, 2012 ; Cong et al, 2013 ; Wang et al, 2013 ). High customizability, high scalability and fine-grained parallelism make FPGAs a good candidate for the development of a neural simulation platform.…”

Section: Introductionmentioning

confidence: 99%

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

2016

View full text Add to dashboard Cite

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

show abstract

FPGA simulation engine for customized construction of neural microcircuits

Cited by 4 publications

References 25 publications

SNNAP: Approximate computing on programmable SoCs via neural acceleration

SNNAP: Approximate computing on programmable SoCs via neural acceleration

Oscillatory neurocomputing with ring attractors: a network architecture for mapping locations in space onto patterns of neural synchrony

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

Contact Info

Product

Resources

About