SNNAP: Approximate computing on programmable SoCs via neural acceleration

Abstract

Many applications that can take advantage of accelerators are amenable to approximate execution. Past work has shown that neural acceleration is a viable way to accelerate approximate code. In light of the growing availability of on-chip field-programmable gate arrays (FPGAs), this paper explores neural acceleration on off-the-shelf programmable SoCs.We describe the design and implementation of SNNAP, a flexible FPGA-based neural accelerator for approximate programs. SNNAP is designed to work with a compiler workflow that configures the neural network's topology and weights instead of the programmable logic of the FPGA itself. This approach enables effective use of neural acceleration in commercially available devices and accelerates different applications without costly FPGA reconfigurations. No hardware expertise is required to accelerate software with SNNAP, so the effort required can be substantially lower than custom hardware design for an FPGA fabric and possibly even lower than current "C-to-gates" highlevel synthesis (HLS) tools. Our measurements on a Xilinx Zynq FPGA show that SNNAP yields a geometric mean of 3.8× speedup (as high as 38.1×) and 2.8× energy savings (as high as 28×) with less than 10% quality loss across all applications but one. We also compare SNNAP with designs generated by commercial HLS tools and show that SNNAP has similar performance overall, with better resource-normalized throughput on 4 out of 7 benchmarks.

EMEURO: A framework for generating multi-purpose accelerators via deep learning

“…These results have demonstrated the impact that a carefully optimized software-based system can have, before introducing the need for specialized hardware. (c) Figure 9: EMEURO was compared against (a) the neural SoC system by Moreau et al [19]. EMEURO's ability to generalize across domains was tested using (b) Conv-1D and (c) Haar.…”

“…Approximate computing is a very diverse field, consisting of both hardware and software systems. Only a few of these works have utilized neural tuning [13,19]. Being software-only and using neural tuning, EMEURO does not directly resemble any other system.…”

“…Being software-only and using neural tuning, EMEURO does not directly resemble any other system. Here we compare against the system proposed by Moreau et al [19], which uses a system-on-a-chip (SoC) with a FPGA for batched NN execution. A batch size of 32 is used for comparison purposes.…”

Towards General-Purpose Neural Network Computing

“…Other architectural parameters were held constant at two Transaction Table entries, four Configuration Cache entries, 32KB of cache storage per entry, and 64 total register elements. Table III shows a list of the NN configurations, taken from recent MLP configurations used in approximate computing [18]- [20], microprocessor state prediction [24], and science [32] applications. Figure 10 shows the average power consumption for each point in the DANA design space.…”

“…In the former, explicit case, one wants to encourage applications and libraries to easily utilize NN facilities in a fine-grained fashion with portability across hardware technologies. In the later, implicit case, compilers and runtime systems should, also portably, exploit available hardware facilities to transparently use NN processing as needed, e.g., stitching in NNs in place of function calls to enact approximations [18]- [20] or exploiting NNs at runtime to model an application's behavior and enable parallel speculations [24].…”