2018 IEEE International Conference on Industrial Technology (ICIT) 2018
DOI: 10.1109/icit.2018.8352387
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FPGA realization of speech encryption based on modified chaotic logistic map

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Cited by 13 publications
(3 citation statements)
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“…Pande and Zambreno [28] have presented a modified logistic map dealing with double floating point precision to increase the Lyapunov exponent and uniformity of bifurcation map, which has been implemented in one of the top family FPGA devices of Xilinx, the Virtex-6. Tolba et al [29] have investigated Speech Encryption using a Virtex-5 using modified logistic map with 3 × registers and 2 × multipliers as well as 2 × adders to deal with 32-bits in fixed-point representation. Dabal and Pelka [30] has adopted logistic map using the expression x n +1 = (4 x n )(1 − x n ) which implies in an extra subtraction operation to perform the (1 − x n ) .…”
Section: Resultsmentioning
confidence: 99%
“…Pande and Zambreno [28] have presented a modified logistic map dealing with double floating point precision to increase the Lyapunov exponent and uniformity of bifurcation map, which has been implemented in one of the top family FPGA devices of Xilinx, the Virtex-6. Tolba et al [29] have investigated Speech Encryption using a Virtex-5 using modified logistic map with 3 × registers and 2 × multipliers as well as 2 × adders to deal with 32-bits in fixed-point representation. Dabal and Pelka [30] has adopted logistic map using the expression x n +1 = (4 x n )(1 − x n ) which implies in an extra subtraction operation to perform the (1 − x n ) .…”
Section: Resultsmentioning
confidence: 99%
“…Table 15 shows the maximum frequency obtained for both encryption designs where the design without key generation and design with key generation achieve a maximum frequency of 616.96 15 based on Virtex-5 FPGA XC5VLX50T. The proposed encryption scheme uses much fewer hardware resources when compared to previous work presented in [14], [15], [53]. Also, the proposed scheme achieved the best throughput among all techniques.…”
Section: A Computational Time Analysismentioning
confidence: 95%
“…Furthermore, discrete chaotic functions are hardware friendly and easy to implement on currently available modules. [12,13,14] .…”
Section: Introductionmentioning
confidence: 99%