FPGA implementation of stereo disparity with high throughput for mobility applications

An efficient hardware architecture for stereo disparity estimation

“…The SAD core is a fully pipelined design. As compared to the similar works [17], [15], [11], our architecture shows a substantial reduction in the utilization of block RAMs, LUTs (Lookup Tables) and registers. Table II shows a detailed performance evaluation of the proposed architecture.…”

“…However all these architectures have to compromise on resource, resolution or on frame rate. Carlos Y Villalpando et.al presented a SAD based FPGA implementation of stereo disparity with high throughput for mobility applications [11]. In this system, the hardware implementation cost is high.…”

“…With a view to reduce the computational complexity of the architecture, we propose a hardware architecture which performs SAD based disparity estimation. The works of [12], [13], [11], [14], [15] show that the SAD algorithm is a simple yet accurate algorithm for stereo matching depth estimation applications. SAD is chosen for demonstrating the capabilities of architecture since our work is concentrated on efficient hardware implementation of window matching algorithm.…”

An FPGA based Stereoptic Image Capture System

“…Stereoptic hardware systems primarily base the quality of the system on the time taken to complete the correspondence (see Section III) algorithm for a single frame [2], [9][10][11][12][13][14]. The frame dimension, and image complexity are therefore key factors in rating the quality of the stereopsis implementation.…”

“…The frame dimension, and image complexity are therefore key factors in rating the quality of the stereopsis implementation. Another important attribute is the quality of the disparity (see Section III) map [11], [13] and [14]. However the disparity map requires both stereo images for an opinion-based visual comparison.…”