FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC

Zhang, Jianfeng; Chow, Paul; Liu, Hengzhu

doi:10.1109/fpt.2015.7393139

Cited by 6 publications

(21 citation statements)

References 21 publications

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“…To make a fair competition with other works, the enhanced unified DCT/IDCT architecture has also been synthesized on a Xilinx Virtex-5 LX110T platform to verify the correctness and performance. Compared to the state-of-the-art DCTs and the latest unified DCT/IDCT architectures, including our previous work [15], the proposed architecture demonstrates better performance.…”

Section: Introductionmentioning

confidence: 85%

“…In the meantime, as DCT and IDCT are usually applied in image and video systems simultaneously, a unified 1-D DCT and IDCT architecture would be very efficient. As the existence of transcendental function calculation for 1-D DCT/IDCT, many acceleration algorithms are proposed, which can be divided into three different kinds, such as multiplier-based algorithms [8], [9], distributed arithmetic (DA) based algorithms [10], [11] and coordinate rotation digital computer (CORDIC) based algorithms [12]- [15]. Even the multiplier-based and the DA-based DCT/IDCT could have high peak signal-to-noise ratio (PSNR) compared with the conventional CORDIC-based method, but they are not well applied because of the high-power consumption and the complicated computation components.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Our previous work [15] only based on adaptive recoding CORDIC (ARC) [18] achieves better performance, but the accuracy of CORDIC based rotation elements can be improved by our latest published work enhanced adaptive recoding CORDIC (EARC) [19]. Meanwhile, our another published paper [22] proposed a novel method that the two different vector rotations share the same CORDIC-based component, and the performance is improved compared with the Huang and the Lee architectures, but is even worse than the one in [15]. Hence, we propose an enhanced unified DCT/IDCT architecture based on the adopting of the efficient decomposition method in this paper, in which the transcendental functions are executed by the cooperation between the conventional CORDIC and EARC to further reduce the computation error, and the scale factor of conventional CORDIC and the compensated scale factor of DCT/IDCT are integrated together, which are realized by the optimized radix-2 scale factor approximation scheme to further cover the cases that the first terms of the quadratic polynomials are 2 −1 to further improve the computation accuracy.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation

et al. 2019

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The Discrete cosine transform (DCT) and inverse Discrete cosine transform (IDCT) have been widely used in image and video compression standards, and more and more researchers focus on the method that taking use of the coordinate rotation digital computer (CORDIC) to execute the DCT and IDCT, the reason is that CORDIC can realize the complex transcendental functions only by using shifters and adders, and is easily suitable implemented in a parallel way. However, the conventional CORDIC has some drawbacks, such as low precision, long iteration number, scale factor and so on. In our previous paper, we have implemented an unified DCT/IDCT based on adaptive recoding CORDIC (ARC) to improve the performance. In this paper, compared with our previous work, we propose an enhanced unified architecture for DCT and IDCT based on the cooperation between the enhanced adaptive recoding coordinate rotation digital computer (EARC) and the conventional CORDIC, in which the radix-2 scale factor approximation proposed in our previous paper is also optimized significantly to achieve better performance in power consumption and PSNR. To conduct a fair competition, the proposed architecture is also validated on a Virtex 5 FPGA platform to evaluate the performance. Under DCT only mode, compared with the Huang and Lee architectures, the proposed architecture at least uses 3.3% less area, dissipates 9% less power at the nearly 2% cost of the critical path delay. Under DCT/IDCT mode, the proposed architecture also saves over 2% hardware resources, reduces more than 5.9% power dissipation when compared to the latest unified DCT/IDCT architectures. Meanwhile, the proposed architecture exceeds the state-of-the-art unified architectures over 0.98 dB in PSNR. Compared with 2S-8P-DCT and 3S-8P-DCT, the proposed unified DCT/IDCT architecture also achieves the best performance in accuracy, processing time and throughput.

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Section: Introductionmentioning

confidence: 85%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation

et al. 2019

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“…The second axe consist on improve the DCT in terms of power consumption ( [5], [6], [7]). In fact, it is well-known that DCT is one of the computationally intensive transforms since it requires many multiplications and additions.…”

Section: Introductionmentioning

confidence: 99%

High Precision DCT CORDIC Architectures for Maximum PSNR

Saad¹,

Hachaı̈chi²,

Lahbib³

et al. 2017

ijacsa

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Abstract-This paper proposes two optimal Cordic Loeffler based DCT (Discrete Cosine Transform algorithm) architectures: a fast and low Power DCT architecture and a high PSNR DCT architecture. The rotation parameters of CORDIC angles required for these architectures have been calculated using a MATLAB script. This script allows the variation of the angle's precision from 10 −1 to 10 −4 . The experimental results show that the fast and low Power DCT architecture correponds to the precision 10 −1 . Its complexity is even lower than the BinDCT which is a reference in terms of low complexity and its power has been enhanced in comparison with the conventional Cordic Loeffler DCT by 12 mW. The experimental results also show that the high PSNR DCT architecture corresponds to the precision 10 −3 for which the PSNR has been improved by 6.55 dB in comparison with the conventional Cordic Loeffler DCT. Then, the hardware implementation and the generated RTL of some required Cordics are presented.

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Enhanced Configurable DCT Cordic Loeffler Architectures for Optimal Power-PSNR Trade-Off

Saad

Lahbib

Hachaı̈chi

2017

J Sign Process Syst

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FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC

Cited by 6 publications

References 21 publications

A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation

A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation

High Precision DCT CORDIC Architectures for Maximum PSNR

Enhanced Configurable DCT Cordic Loeffler Architectures for Optimal Power-PSNR Trade-Off

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