FPGA Implementation of LDPC Encoder Architecture for Wireless Communication Standards

Goriushkin, Ruslan; Nikishkin, Pavel; Ovinnikov, Aleksei; Likhobabin, Evgeny; Vityazev, Vladimir

doi:10.1109/mocast49295.2020.9200293

Cited by 3 publications

(1 citation statement)

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“…In [ 11 ], a fully parallel QC-LDPC encoder based on a reduced complexity XOR tree designed specifically for the IEEE 802.11n standard was proposed. In [ 12 ], a pipeline architecture for QC-LDPC encoder was proposed. The design can be easily reconstructed to support variable code rates and code lengths through parameter configuration.…”

Section: Introductionmentioning

confidence: 99%

Low-Latency QC-LDPC Encoder Design for 5G NR

Tian

Bai

Liu

2021

Sensors

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In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel structure to obtain multiple parity check bits and thus reduce encoding latency significantly. The proposed encoder maps high parallelism encoding algorithms to a configurable circuit architecture, achieving flexibility and support for all 5G NR code length and code rate. The experimental results show that under the 800 MHz system frequency, the achieved data throughput ranges from 62 to 257.9 Gbps, and the maximum code length encoding time under base graph 1 (BG1) is only 33.75 ns, which is the critical encoding time of our proposed encoder. Finally, our proposed encoder was synthesized on SMIC 28 nm CMOS technology; the result confirmed the effectiveness and feasibility of our design.

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Section: Introductionmentioning

confidence: 99%