FPGA Implementation of Laplacian of Gaussian Edge Detection Algorithm

Abstract

This paper introduces a design of gaussian Laplace edge detection algorithm model based on system generator which can be realized in FPGA.The data of a two- dimensional image was changed into a one-dimensional array，before line buffering in two Dual port RAM,the convolution of the image pixel data and the LOG template was carried out in the modules constituted of the component elements such as AddSub, Shift and Delay . After getting the absolute value with the modules of Slice，Negate and Mux ，the output was the image after edge-detection .The module function and the selecting principle was analyzed from the point of view of saving FPGA resources.The WaveScope and resource estimator showed that ：not only the detection result and the running speed was guaranteed but also the FPGA resources can be saved .

Sensor Signal Processing using High-Level Synthesis and Internet of Things with a Layered Architecture

“…In this paper embedded PEs with four layer new design framework architecture is proposed to sense the devises of IOT applications with the support of high-level synthesis DBMF (database management function) tool [8,17,19]. It exploits the repetitive high level synthesis process.…”

“…Fixed bit widths of data paths, elementary blocks, and switch matrices aiming at mass production of the devices were one example of the inefficiency. Sensors used in IOT applications have various data interfaces, such as 8, 12, 14, or 16 bits [ 17,19]. Predefined data path between arrays of arithmetic logic units prevents behavioural synthesis tools from the optimization of layout size and the reduction in power consumption.…”

“…Predefined data path between arrays of arithmetic logic units prevents behavioural synthesis tools from the optimization of layout size and the reduction in power consumption. Therefore, optimized Arithmetic Logic Units (ALU) and flexible data paths are required to embed processors in sensor units [13,[15][16][17].…”