FPGA implementation of high performance digital down converter for software defined radio

Datta, Debarshi; Mitra, Partha P.; Dutta, Himadri Sekhar

doi:10.1007/s00542-019-04579-w

Cited by 17 publications

(7 citation statements)

References 18 publications

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“…2. The polyphase component operates at a speed of fs/R1, resulting in the polyphase CORDIC processor being more feasible in the FPGA platform [10]. To achieve correct output, the relation between fs and R1 is expressed as…”

Section: Polyphase Cordic Processormentioning

confidence: 99%

Area and power-efficient reconfigurable digital down converter on FPGA

Datta

Dutta

2022

FACTA U EE

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This paper presents a field-programmable gate array (FPGA)-based digital down converter (DDC) that can reduce the bandwidth from about 70 MHz to 182.292 kHz. The proposed DDC consists of a polyphase COordinate Rotation DIgital Computer (CORDIC) processor and a multirate filter. The advantage of polyphase CORDIC processor is to process with high sample rate input data and produces computational efficient noiseless baseband spectrum. The pipeline multirate filter works at a high clock speed. Moreover, the multirate filter generates a fractional sample rate factor using a cubic B-spline Farrow filter. The proposed DDC is coded with optimal hardware description language (HDL) and tested on Kintex-7 Xilinx FPGA as the target device. Experimental results indicate that the proposed design saves chip area, power consumption and operates at high speed without loss of any functionality. Additionally, the proposed design offers sufficient spurious-free dynamic range (SFDR) and produces less than 1 Hz frequency resolution at the output.

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Section: Polyphase Cordic Processormentioning

confidence: 99%

Area and power-efficient reconfigurable digital down converter on FPGA

Datta

Dutta

2022

FACTA U EE

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“…Datta et al [3] proposed an efficient FPGA-based design for digital downconversion, specifically tailored for software-defined radio applications. The efficient application of digital filters on FPGA platforms was designed [4,5].…”

Section: Introductionmentioning

confidence: 99%

Enhanced Signal Processing Through FPGA-Based Digital Downconversion via the CORDIC Algorithm

Yin,

Jiang

2024

JII

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To address the rate matching issue between high-bandwidth and high-sampling-rate analog-to-digital converters (ADCs) and low-bandwidth and low-sampling-rate baseband processors, the key technology of digital downconversion is introduced. This approach relocates the intermediate-frequency baseband signal to a vicinity of the baseband, laying a foundation for subsequent Digital Signal Processor (DSP) analysis and processing. In an innovative application of the Coordinate Rotation Digital Computer (CORDIC) algorithm for Numerically Controlled Oscillator (NCO) in a pipeline design, the phase differences of five parallel signals are measured, facilitating real-time parallel processing of the phase and amplitude relationships of multiple signals. The Field Programmable Gate Array (FPGA) design and implementation of the digital mixer module and filter bank for digital downconversion have been accomplished. A test board for the direction-finding application of five digital downconversion channels has been constructed, with the FMQL45T900 as its core. The correctness of the direction-finding data has been validated through practical application, demonstrating a significant improvement in power consumption compared to methods documented in other literature, thereby enhancing overall efficiency. The digital downconversion technology based on the CORDIC algorithm is applicable in various fields, including military communications, broadcasting, and radar navigation systems.

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“…Many new designs and software products have recently been proposed using field-programmable gate arrays (FPGAs) as hardware for DSP systems because of the technology's extremely high performance and flexibility [12]. Now that FPGAs are equipped with gigabit serial communications, memory interfaces, embedded processors, and a wide range of core firmware modules, this is even more relevant than before [13]. Various signal processing applications can be performed simultaneously on this card, including laser beam communication [14].…”

Section: Introductionmentioning

confidence: 99%

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

Marimuthu¹,

Rajendran²,

Radhakrishnan³

et al. 2023

Computers, Materials &Amp; Continua

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Continuous improvements in very-large-scale integration (VLSI) technology and design software have significantly broadened the scope of digital signal processing (DSP) applications. The use of application-specific integrated circuits (ASICs) and programmable digital signal processors for many DSP applications have changed, even though new system implementations based on reconfigurable computing are becoming more complex. Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation (DWT) and sophisticated computerized design techniques, which are much needed in today's modern world. New research and commercial efforts to sustain power optimization, cost savings, and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged. Hence, in this paper, it is proposed that the DWT method can be implemented on a fieldprogrammable gate array in a digital architecture (FPGA-DA). We examined the effects of quantization on DWT performance in classification problems to demonstrate its reliability concerning fixed-point math implementations. The Advanced Encryption Standard (AES) algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks (ANN) method. By reducing hardware area by 57%, the proposed system has a higher throughput rate of 88.72%, reliability analysis of 95.5% compared to the other standard methods.

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FPGA implementation of high performance digital down converter for software defined radio

Cited by 17 publications

References 18 publications

Area and power-efficient reconfigurable digital down converter on FPGA

Area and power-efficient reconfigurable digital down converter on FPGA

Enhanced Signal Processing Through FPGA-Based Digital Downconversion via the CORDIC Algorithm

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

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