FPGA Implementation of Hardware Accelerator for Real-time Video Image Edge Detection

In this paper a novel low-power approximate floating-point multiplier is presented. Since the mantissa computation is responsible for the largest part of the power consumption, we apply a novel approximation technique to mantissa multiplication, based on static segmentation. In our approach, the inputs of the mantissa multiplier are properly segmented so that a small inner multiplier can be used to calculate the output, with beneficial impact on power and area. To further improve performance, we introduce a novel segmentation-and-truncation approach which allows us to eliminate the shifter normally present at the output of the segmented multiplier. In addition, a simple compensation term for reducing approximation error is employed. The accuracy of the circuit can be tailored at the design time, by acting on a single parameter. The proposed approximate floating-point multiplier is compared with the state-of-the-art, showing good performance in terms of both precision and hardware saving. For single-precision floating-point format, the obtained NMED is in the range 10−5–7 × 10−7, while MRED is in the range 3 × 10−3–1.7 × 10−4. Synthesis results in 28 nm CMOS show area and power saving of up to 82% and 85%, respectively, compared to the exact floating-point multiplier. Image processing applications confirm the expectations, with results very close to the exact case.

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FPGA Implementation of Hardware Accelerator for Real-time Video Image Edge Detection

Cited by 3 publications

References 9 publications

Performance Evaluation of Real-Time Video Processing Edge Detection on Various Platforms

Performance Evaluation of Real-Time Video Processing Edge Detection on Various Platforms

High Performance VLSI Architecture for Real-Time Video Edge Detection

Approximate Floating-Point Multiplier based on Static Segmentation

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