FPGA implementation of hamming code for increasing the frame rate of CAN communication

Design and implementation of single bit error correction linear block code system based on FPGA

“…-Position 1: check 1 bit, skip 1 bit, check 1 bit, skip 1 bit, etc. (1,3,5,7,9,11,13,15 and so on for the position 16 and 32 …etc. e. Set a Parity bit to 1 if the total number of ones in the positions it checks is odd (XOR operation between all bits) .…”

“…The transmission systems are exposing to get bits error values in either the instruction or data causing undesirable crashes or other system failures. Therefore, utilizing Hamming Code inside an embedded system is considered with high priority in modern industrial fields [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19].…”

“…Hamming code as hardware system using VHDL or Virlog as hardware description language is proposed to demonstrate and analyze the performance of the system. Most of these works have limitation on the number of data bits and hardware resources [7][8][9][10][11][12][13][14][15][16][17][18][19]. Literary review for the most important research involved this approaches with their limitation can be summarized: -ECC application on embedded systems is designed for memory error detection and correction it is realized a 64-bit ECC controller has been proposed in [10].…”

“…-Design a Hamming code system based on IP core with 56 data bits for the transmission data of communication system is demonstrated in [14]. -Hamming code architecture which is used as an alternative error detection code scheme in Controller Area Network technology, the implementation done on set of inputs from 8-bit to 64-bit of data frames has been explained in [15]. -A code rate of (15,11) algorithm for design Hamming code as hardware system is utilized in [16], while a code rate of (7,4) algorithm is used in with Verilog as hardware description languge [17].…”