Abstract. The multifactor optical encryption authentication method [Opt. Lett., 31, 721-3 (2006)] reinforces optical security by allowing the simultaneous authentication of up to four factors. In this work, the photon-counting imaging technique is applied to the multifactor encrypted function so that a sparse phase-only distribution is generated for the encrypted data. The integration of both techniques permits an increased capacity for signal hiding with simultaneous data reduction for better fulfilling the general requirements of protection, storage and transmission. Cryptanalysis of the proposed method is carried out in terms of chosen-plaintext and chosen-ciphertext attacks. Although the multifactor authentication process is not substantially altered by those attacks, its integration with the photon-counting imaging technique prevents from possible partial disclosure of any encrypted factor, thus increasing the security level of the overall process. Numerical experiments and results are provided and discussed.
An optical double-image encryption and authentication method by sparse representation is proposed. The information from double-image encryption can be integrated into a sparse representation. Unlike the traditional double-image encryption technique, only sparse (partial) data from the encrypted data is adopted for the authentication process. Simulation results demonstrate that the correct authentication results are achieved even with partial information from the encrypted data. The randomly selected sparse encrypted information will be used as an effective key for a security system. Therefore, the proposed method is feasible, effective, and can provide an additional security layer for optical security systems. In addition, the method also achieved the general requirements of storage and transmission due to a high reduction of the encrypted information.
Linear block code (LBC) is an error detection and correction code that is widely used in communication systems. In this paper a special type of LBC called Hamming code was implemented and debugged using FPGA kit with integrated software environments ISE for simulation and tests the results of the hardware system. The implemented system has the ability to correct single bit error and detect two bits error. The data segments length was considered to give high reliability to the system and make an aggregation between the speed of processing and the hardware ability to be implemented. An adaptive length of input data has been consider, up to 248 bits of information can be handled using Spartan 3E500 with 43% as a maximum slices utilization. Input/output data buses in FPGA have been customized to meet the requirements where 34% of input/output resources have been used as maximum ratio. The overall hardware design can be considerable to give an optimum hardware size for the suitable information rate.
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