FPGA implementation of fast running FIR filters

Rengaprakash, S.; Vignesh, M.; Anwar, Nizirwan; Pragadheesh, M.; Senthilkumar, E; Sandhya, M.; Manikandan, J

doi:10.1109/wispnet.2017.8299970

Cited by 10 publications

(2 citation statements)

References 23 publications

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“…In the literature, it is noted that various digital filters [8][9][10][11][12][13][14][15][16] are designed with variable cut-off frequency. These filters are tuneable [9,10,17] with variable coefficient methodology or fixed coefficient with decimation [9].…”

Section: Necessity Of a Variable Data Rate Transmissionmentioning

confidence: 99%

Dynamically tuneable pre‐modulation filter for an airborne PCM/FM telemetry system

Karnati

Bopanna

Jahagirdar

2021

IET Circuits, Devices & Systems

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In the conventional airborne telemetry system, the pre-modulation filter with a multipole active Bessel filter is preferred to use in Pulse Code Modulator (PCM)/FM transmission. In the existing system, it is not possible to change the cutoff frequency for different data rates dynamically as required in the launch scenario of a long-range aerospace vehicle. In general, aerospace vehicle has multiple propellant stages to travel a desired trajectory path. Each stage gets separated from the vehicle at different instances. Each stage measurement plan is defined and correspondingly the PCM format is generated with an optimum data rate. Hence, the telemetry system is required to transmit variable data rates at various instances of a long-range aerospace vehicle from launch point to end point of a vehicle. This can be addressed by designing a dynamically tuneable pre-modulation (DTPM) filter. Here, a suitable DTPM filter scheme is proposed to mitigate variable data rate transmission in the telemetry system. The scheme is analysed as per IRIG-106 standard and simulated using MATLAB. The same has been modelled using VHDL and implemented targeting 28 nm technology Xilinx Zynq FPGA device. How to cite this article: Karnati SR, Bopanna L, Jahagirdar DR. Dynamically tuneable pre-modulation filter for an airborne PCM/FM telemetry system. IET

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Section: Necessity Of a Variable Data Rate Transmissionmentioning

confidence: 99%

Dynamically tuneable pre‐modulation filter for an airborne PCM/FM telemetry system

Karnati

Bopanna

Jahagirdar

2021

IET Circuits, Devices & Systems

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“…At first the equipment executions of electronic cochlea models utilized simple VLSI as the usage medium because of their little region, fast, and low force utilization. Sarpeshkar actualized the cochlea model as ultra low force programmable simple bionic ear processor [3].Ngamgham et al [4] implemented an eighth order analog filter in state space approach which occupied less area and consumed ultra low power. The speech processor part is the core of the gadget that models electronically, cochlea of the ear.…”

Section: Introductionmentioning

confidence: 99%

Analysis and Implementation of Hybrid FIR Architecture in Speech Processor

Timande¹

2018

IJNPME

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Hearing aid is an electronic gadget precisely used into the internal ear which reestablishes halfway hearing to smooth hearing. The discourse processor of CI parts the sound-related sign into groups of various frequencies and changes over them into appropriate codes for animating the cathodes in cochlea of ear. The cathode actuates sound-related nerve filaments to give hearing sensation. The expense of the CI alone goes to around 100,000 US dollars. For the efficient less well-to-do individuals with hearing sickness, it might be too exorbitant to even consider affording for this hardware to recoup from the conference misfortune. It gets important to cut down the expense. The cost decrease might be accomplished with diminished region, low force and rapid activity of the CI. This goal intuited both the simple and the computerized based CI originators to inquire about their techniques to give individuals less expensive and profoundly understandable CI. The primary objective of this paper is to develop reconfigurable DSP architectures for the filter banks in speech processor of CI with the following features like minimized area of the filter, reduced power consumption of the speech processor and enhanced presentation of the filter. This paper involves the design and hardware implementation of narrow band pass FIR filter for speech processor of CI using the Xilinx System Generator (XSG) tool on Virtex 7 FPGA.

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