FPGA implementation of efficient vedic multiplier

Abstract

Multipliers play a major role in todays digital signal processing and various other applications. Both signed and unsigned multiplications are required in many computing applications. This work proposes the design of efficient signed multiplier using Vedic mathematics in which the calculation of partial product is done using carry select adder (CSeA), which results in less combinational path delay. Signed multiplier architecture is based on two's complement circuit and unsigned Vedic multiplier. In this work, Urdhva Triyakbhyam sutra is used for binary multiplication. To prove the effectiveness of proposed method, the results obtained with conventional multiplier is compared with proposed work in terms of combinational path delay. From the results presented, it is observed that the proposed method gives less path delay as compared to existing methods. Further, the VHDL coding of signed multiplier is done in Xilinx Synthesis Tool (v14.1) and simulated using Modelsim simulator also FPGA implementation of the same is done on Spartan 6 (XC6SLX150T device, FGG900 package, -2 speed grade) and output is displayed on LCD of Spartan 6.

Pipelined vedic multiplier with manifold adder complexity levels

“…This technique uses 'Vertical and Crosswise' methodology which utilizes least delay, and allows for low hardware usage during processing [11]. Thus UT Sutra allows for parallel processing and provides better performance [12][13][14].…”