FPGA Implementation of ECC: Low-Cost Countermeasure against Horizontal Bus and Address-Bit SCA

Kabin, Ievgen; Kreiser, Dan; Dyka, Zoya; Langendoerfer, Peter

doi:10.1109/reconfig.2018.8641732

Cited by 13 publications

(20 citation statements)

References 7 publications

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“…for 4 MHz (see section II) and for 100 MHz using the design synthesized with the compiler option "default". We performed the statistical analysis of the trace measured for the kP operation running at a frequency of 100 MHz using the comparison to the mean as described in [5]. As mention above, the placement of the EM probe was exactly the same for both measurements.…”

Section: A Attack Results Depend On the Frequencymentioning

confidence: 99%

On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal Attack

Kabin

Sosa

Dyka

et al. 2019

2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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This paper reports about the impact of compiler options on the resistance of cryptographic implementations against side channel analysis attacks. We evaluated four compiler option for six different FPGAs from Intel and Xilinx. In order to ensure fair assessment we synthesized always the same VHDL code, kept the measurement setup and statistical analysis method etc. constant. Our analysis clearly shows that the compiler options have an impact on the success of attacks but also that the impact is unpredictable not only between different FPGAs but also for an individual FPGA.

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Section: A Attack Results Depend On the Frequencymentioning

confidence: 99%

On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal Attack

Kabin

Sosa

Dyka

et al. 2019

2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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“…We are aware of some issues of the Montgomery ladder. It is vulnerable to the horizontal Address Bit attack which was presented in [3,16]. The main leakage source is the key dependent addressing of the registers in the algorithm.…”

Section: Discussionmentioning

confidence: 99%

“…The modification done in Algorithm 2 in comparison to the Algorithm 1 refers to the initialization phase and the processing of k l−2 . The operation flow for processing k l−2 (see lines 2-8 in Algorithm 2) differs from the operation flow in the main loop (see lines [9][10][11][12][13][14][15][16][17]. The processing of key bit k l−2 consists of 5 multiplications, 5 squarings, 3 additions and 8 write to register operations, independent of the value of k l−2 .…”

Section: Our Implementation Of the Montgomery Kpmentioning

confidence: 99%

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Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice

et al. 2021

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The Montgomery kP algorithm i.e. the Montgomery ladder is reported in literature as resistant against simple SCA due to the fact that the processing of each key bit value of the scalar k is done using the same sequence of operations. We implemented the Montgomery kP algorithm using Lopez-Dahab projective coordinates for the NIST elliptic curve B-233. We instantiated the same VHDL code for a wide range of clock frequencies for the same target FPGA and using the same compiler options. We measured electromagnetic traces of the kP executions using the same input data, i.e. scalar k and elliptic curve point P, and measurement setup. Additionally, we synthesized the same VHDL code for two IHP CMOS technologies, for a broad spectrum of frequencies. We simulated the power consumption of each synthesized design during an execution of the kP operation, always using the same scalar k and elliptic curve point P as inputs. Our experiments clearly show that the success of simple electromagnetic analysis attacks against FPGA implementations as well as the one of simple power analysis attacks against synthesized ASIC designs depends on the target frequency for which the design was implemented and at which it is executed significantly. In our experiments the scalar k was successfully revealed via simple visual inspection of the electromagnetic traces of the FPGA for frequencies from 40 to 100 MHz when standard compile options were used as well as from 50 MHz up to 240 MHz when performance optimizing compile options were used. We obtained similar results attacking the power traces simulated for the ASIC. Despite the significant differences of the here investigated technologies the designs’ resistance against the attacks performed is similar: only a few points in the traces represent strong leakage sources allowing to reveal the key at very low and very high frequencies. For the “middle” frequencies the number of points which allow to successfully reveal the key increases when increasing the frequency.

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“…The strong SCA leakage sources are the addressing of registers and the activity of the bus. Details are described in [21]. For the design D_ultra, i.e.…”

Section: Performed Attack Using the Comparison To The Meanmentioning

confidence: 99%

Horizontal Attacks Against ECC: From Simulations to ASIC

Kabin

Dyka

Klann

et al. 2020

Lecture Notes in Computer Science

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In this paper we analyse the impact of different compile options on the success rate of side channel analysis attacks. We run horizontal differential side channel attacks against simulated power traces for the same kP design synthesized using two different compile options after synthesis and after layout. As we are interested in the effect on the produced ASIC we also run the same attack against measured power traces after manufacturing the ASIC. We found that the compile_ultra option reduces the success rate significantly from 5 key candidates with a correctness of between 75 and 90 per cent down to 3 key candidates with a maximum success rate of 72 per cent compared to the simple compile option. Also the success rate after layout shows a very high correlation with the one obtained attacking the measured power and electromagnetic traces, i.e. the simulations are a good indicator of the resistance of the ASIC.

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FPGA Implementation of ECC: Low-Cost Countermeasure against Horizontal Bus and Address-Bit SCA

Cited by 13 publications

References 7 publications

On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal Attack

On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal Attack

Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice

Horizontal Attacks Against ECC: From Simulations to ASIC

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