FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping

Soliman, Shady M.; Jaela, Mohammed A.; Abotaleb, Abdelrhman M.; Hassan, Youssef S.; Abdelghany, Mohamed; Abdel-Hamid, Amr T.; Salama, Khaled N.; Mostafa, Hassan

doi:10.1016/j.vlsi.2019.06.004

Cited by 20 publications

(9 citation statements)

References 4 publications

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“…The comparison is between the reconfiguration time of the three algorithms used in the state-of-the-art design and the presented design. First, the results of the reconfiguration time of the presented design in comparison with the reconfiguration time in the state-of-the-art design [3] are as illustrated in Figure 10. The comparison is between the reconfiguration time of the three algorithms used in the state-of-the-art design and the presented design.…”

Section: Results Of the Presented Designmentioning

confidence: 99%

“…When used for small messages, it has the best performance [15]. DEOXYS-II operates in two modes: the first mode is nonce respecting and the second mode is nonce misuse resistant [3]. In the proposed design, the nonce misuse resistant mode is employed to be able to reuse the same N with the same key without facing any danger of ciphertext extraction.…”

Section: Deoxysmentioning

confidence: 99%

“…Consequently, mobile phones can be used to manage the devices easily [2]. The number of IoT devices is rapidly increasing and it is predicted to exceed 18 billion by 2022 [3]. However, as the number of IoT-connected devices increases, so does the amount of the gathered data by IoT systems.…”

Section: Introductionmentioning

confidence: 99%

“…In Soliman et al [3], the authors introduced a security system design that used the algorithm hopping technique, which is derived from the frequency hopping technique. The design interchanges between five lightweight cryptographic algorithms in a random manner using the algorithm hopping technique where the swap is performed using dynamic partial reconfiguration.…”

Section: Introductionmentioning

confidence: 99%

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High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

2021

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IoT technology is evolving at a quick pace and is becoming an important part of everyday life. Consequently, IoT systems hold large amounts of data related to the user of the system that is vulnerable to security breaches. Thus, data collected by IoT systems need to be secured efficiently without affecting the IoT systems’ performance and without compromising security as well. In this paper, a high-performance dynamic security system is introduced. The system makes use of the ZedBoard’s dynamic partial reconfiguration capability to shift between three distinct cipher algorithms: AEGIS, ASCON, and DEOXYS-II. The switching between the three algorithms is performed using two different techniques: the algorithm hopping technique or the power adaptive technique. The choice of which technique to be used is dependent on whether the system needs to be focused on performance or power saving. The ciphers used are the CAESAR competition finalists that achieved the greatest results in each of the three competition categories, where each cipher algorithm has its own set of significant characteristics. The proposed design seeks to reduce the FPGA reconfiguration time by the application of LZ4 (Lempel-Ziv4) compression and decompression techniques on the ciphers’ bitstream files. The reconfiguration time decreased by a minimum of 38% in comparison to the state-of-the-art design, while the resource utilization increased by approximately 2%.

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Section: Results Of the Presented Designmentioning

confidence: 99%

Section: Deoxysmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

2021

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“…The use of FPGAs within data centres, has enabled efficient acceleration of operations such as data/feature extraction, dataflow management and information analysis [1], for a range of applications including image recognition [2], in-network security [3] and machine learning [4], among others. However this virtualisation introduces considerable overheads in latency, bandwidth and resource consumption with respect to the volume of data being processed [5].…”

Section: Introductionmentioning

confidence: 99%

Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration

Bucknall

Shreejith

Fahmy

2019

2019 International Conference on Field-Programmable Technology (ICFPT)

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Partial reconfiguration supports virtualisation of applications on FPGAs, enabling compute to dynamically adapt to workloads in distributed infrastructure and datecenters. While the latter often makes use of the PCIe interface and supporting infrastructure to allocate and load compute kernels via a host CPU, FPGAs are becoming increasingly popular as standalone resources in edge-computing, requiring them to manage accelerators autonomously. This paper presents a platform that supports the managing of accelerator bitstreams over the network interface on a Xilinx Zynq device without intervention by the Arm processor. We compare against traditional vendor provided PR management for both library accelerators and custom accelerators and show that we achieve a 29% decrease in reconfiguration trigger latency using this approach.

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FPGA/AI-Powered Data Security for IoT Edge Computing Platforms: A Survey and Open Issues

Pham-Quoc

2023

Intelligence of Things: Technologies and Applications

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FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping

Cited by 20 publications

References 4 publications

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration

FPGA/AI-Powered Data Security for IoT Edge Computing Platforms: A Survey and Open Issues

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