Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration

Abstract

Partial reconfiguration supports virtualisation of applications on FPGAs, enabling compute to dynamically adapt to workloads in distributed infrastructure and datecenters. While the latter often makes use of the PCIe interface and supporting infrastructure to allocate and load compute kernels via a host CPU, FPGAs are becoming increasingly popular as standalone resources in edge-computing, requiring them to manage accelerators autonomously. This paper presents a platform that supports the managing of accelerator bitstreams over the network interface on a Xilinx Zynq device without intervention by the Arm processor. We compare against traditional vendor provided PR management for both library accelerators and custom accelerators and show that we achieve a 29% decrease in reconfiguration trigger latency using this approach.

Design of an energy-efficient nonvolatile lookup table circuit using active-load-localized circuitry with self-terminated writing/reading

“…Because users can implement their desired hardware immediately by just changing the configuration data, FPGA-based design can follow up exponential growth of IoT applications. 4,5) Especially, FPGA is an important hardware platform for neural-network-based artificial-intelligence applications where massively parallel matrix computation is required. [6][7][8][9][10][11][12] In spite of the great potential of the FPGA, a inevitable standby power issue 13) exists in the conventional SRAM-based FPGA.…”

Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

“…[1][2][3] A fieldprogrammable gate array (FPGA) is a promising hardware platform for edge computing owing to its reconfigurable and fully parallel architecture. [4][5][6][7] A hardware accelerator for artificial intelligence (AI) plays a significant role in such edge computing. 8,9) The FPGA is a well-suited hardware platform for the "edge-AI" accelerator.…”

Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting

“…[5][6][7] In particular, a field-programmable gate array (FPGA) is a well-suited hardware platform for implementing a BCNN accelerator owing to its reconfigurable and fully parallel architecture. [8][9][10][11][12][13] Since the optimum network structure of the BCNN depends on the application and the BCNN computation method itself continues advancing, reconfigurability of the FPGA is suitable for implementing a BCNN accelerator. On the other hand, the standby power consumption due to the leakage current is a critical issue for a conventional static-random-accessmemory (SRAM)-based FPGA.…”