FPGA Implementation of DLP-PHOTON Hash Function

Hammad, Baraa Tareq; Abbas, Yasir Amer; Jamil, Norziana; Rusli, Mohd Ezanee; Z’aba, Muhammad Reza

doi:10.14257/ijfgcn.2017.10.12.07

Cited by 5 publications

(7 citation statements)

References 14 publications

(18 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This architecture achieves better trade-offs between performance and utilization of the logic area than other existing works. Therefore, the proposed architecture outperforms the existing works and achieves higher efficiency except for the case of [16] as they achieved higher efficiency at the cost of a huge area because their implementation of PHOTON was in double-length Sponge construction. For Spartan-3, an efficiency of 0.99 was achieved and it is much better than all the existing implementations except for the design proposed by [16] with a slightly higher efficiency because their implementation is for high performance at the cost of 3x higher resources utilization.…”

Section: Resultsmentioning

confidence: 90%

“…Therefore, the proposed architecture outperforms the existing works and achieves higher efficiency except for the case of [16] as they achieved higher efficiency at the cost of a huge area because their implementation of PHOTON was in double-length Sponge construction. For Spartan-3, an efficiency of 0.99 was achieved and it is much better than all the existing implementations except for the design proposed by [16] with a slightly higher efficiency because their implementation is for high performance at the cost of 3x higher resources utilization. The implementations on Artix-7 and Kintex-7 achieve almost double the efficiency of the benchmarking architectures, with the same exception mentioned earlier for the design proposed in [16].…”

Section: Resultsmentioning

confidence: 90%

“…For Spartan-3, an efficiency of 0.99 was achieved and it is much better than all the existing implementations except for the design proposed by [16] with a slightly higher efficiency because their implementation is for high performance at the cost of 3x higher resources utilization. The implementations on Artix-7 and Kintex-7 achieve almost double the efficiency of the benchmarking architectures, with the same exception mentioned earlier for the design proposed in [16].…”

Section: Resultsmentioning

confidence: 92%

“…Therefore, encryption/decryption and authentication engines should be designed with the least possible logic resources and the highest possible throughput to satisfy the constraints of the IoT edge devices. Several PHOTON hash function architectures of different design optimization goals were presented in [5], [16], [23] and implemented on Spartan3, Virtex5, Artix7 and Kintex7 FPGAs from Xilinx. The implementations of these existing designs utilize large amount of logic resources relative to the achieved performance.…”

Section: Resultsmentioning

confidence: 99%

“…In the original paper of PHOTON hash function [4], the architecture was hardware-oriented and explored in Application Specific Integrated Circuit (ASIC) with the gate equivalent as the main parameter for area utilization. Lately, the design space exploration of PHOTON hash function was proposed by [5], [16], [17] on FPGA targeting different FPGA devices. The main limitation of the existing PHOTON architectures is the large utilization of logic area compared to the achieved frequency and throughput.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices

et al. 2020

View full text Add to dashboard Cite

The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHO-TON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26% to 51.04% in the speed performance and a reduction rate of 7.55% to 60.64% in area utilization compared to existing implementations of PHOTON hash functions.

show abstract

Section: Resultsmentioning

confidence: 90%