FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine

Hassan, Hanan M.; Shalash, Ahmed F.; Mohamed, Kartini

doi:10.1109/iscas.2011.5937798

Cited by 4 publications

(10 citation statements)

References 16 publications

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“…In this way, the ASIP is not merely limited to linear algorithms, and users have a flexibility to implement their own design. This is the unique advantage compared with other existing ASIP designs [38], [39].…”

Section: Instruction Setmentioning

confidence: 95%

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics

Yao

Zhang

et al. 2015

IEEE/ACM Trans. Comput. Biol. and Bioinf.

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Neural coding is an essential process for neuroprosthetic design, in which adaptive filters have been widely utilized. In a practical application, it is needed to switch between different filters, which could be based on continuous observations or point process, when the neuron models, conditions, or system requirements have changed. As candidates of coding chip for neural prostheses, low-power general purpose processors are not computationally efficient especially for large scale neural population coding. Application specific integrated circuits (ASICs) do not have flexibility to switch between different adaptive filters while the cost for design and fabrication is formidable. In this research work, we explore an application specific instruction set processor (ASIP) for adaptive filters in neural decoding activity. The proposed architecture focuses on efficient computation for the most time-consuming matrix/vector operations among commonly used adaptive filters, being able to provide both flexibility and throughput. Evaluation and implementation results are provided to demonstrate that the proposed ASIP design is area-efficient while being competitive to commercial CPUs in computational performance.

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Section: Instruction Setmentioning

confidence: 95%

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics

Yao

Zhang

et al. 2015

IEEE/ACM Trans. Comput. Biol. and Bioinf.

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“…At the same time, we satisfy the requirements of the supported systems, such as throughput, power, area, and so on. We build on our work presented in [8][9][10][11], where we presented the individual ASIPs supporting FFT, channel estimation and synchronisation. Here, we present the implementation of the entire symbol chain, dealing with the issues of integration, accessibility and performance.…”

Section: Paper Overviewmentioning

confidence: 99%

Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor

All¹,

Hassan²,

Hamdy³

et al. 2015

IET Circuits, Devices & Systems

Self Cite

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The two implementation choices for the baseband part of wireless radios are the application-specific platforms (e.g. application-specific integrated circuits (ASICs)) and the programmable processors (e.g. digital signal processors (DSPs)). An application-specific instruction-set processor (ASIP) is a customised processor that bridges the gap between the two platforms. In this work, a novel implementation of the signal processing part of an orthogonal frequency division multiplexing (OFDM) baseband processor using three ASIPs is presented. The ASIPs provide novel architectures for the symbol chain, including fast Fourier transform, channel estimation subsystem and synchronisation subsystem. This design provides a close to DSPs level of flexibility, making it suitable for supporting all the modes of a large number of OFDM standards. In the meantime, the system maintains a performance level comparable to ASICs. This is demonstrated by providing post-layout results for 0.13 μm Taiwan semiconductor manufacturing company complementary metal-oxide semiconductor technology.

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“…We build on previous studies in [9,10] where we presented a memory based architecture controlled by an instruction set processor. In this study we combine all elements of the design: performing further optimization on the processing elements (PE) to increase their flexibility and performance; as well as presenting a complete implementation including the full memory map and the programming front-end.…”

Section: Paper Overviewmentioning

confidence: 99%

“…Each of the above techniques have drawbacks to different degrees like lower throughput, power or both. In [10] we proposed an address scheme to solve the above problem with conflictfree memory access. The scheme is contingent on partitioning the memory to 4 dual-port memory banks as well as the specific way data is distributed between the banks.…”

Section: Read and Write Address Generatorsmentioning

confidence: 99%

Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine

2012

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In this article we present an ASIP design for a discrete fourier transform (DFT)/discrete cosine transform (DCT)/finite impulse response filters (FIR) engine. The engine is intended for use in an accelerator-chain implementation of wireless communication systems. The engine offers a very high degree of flexibility, accepting and accelerating performance approaches that of any-number DFT and inverse discrete fourier transform, one and two dimension DCT, and even general implementations of FIR equations. Performance approaches that of dedicated implementations of such algorithms. A customized yet flexible redundant memory map allows processor-like access while maintaining the pipeline full in a dedicated architecture-like manner. The engine is supported by a proprietary software tool that automatically sets the rounding pattern for the accelerator rounder to maintain a required signal to quantization noise or output RMS for any given algorithm. Programming of the processor is done through a mid-level language that combines register-specific instructions with DFT/DCT/FIR specificinstructions. Overall the engine allows users to program a very wide range of applications with software-like ease, while delivering performance very close to hardware. This puts the engine in an excellent spot in the current wireless communications environment with its profusion of multi-mode and emerging standards.

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FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine

Cited by 4 publications

References 16 publications

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics

Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor

Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine

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