FPGA implementation of a 3GPP turbo codec

Steensma, J.; Dick, Chris

doi:10.1109/acssc.2001.986881

Cited by 4 publications

(1 citation statement)

References 4 publications

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“…A number of implementations addressed various turbo decoders achieving medium throughput figures [60], [61], [62], [56].…”

Section: Standards and Productsmentioning

confidence: 99%

VLSI for Turbo Codes

Masera

Turbo Code Applications

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The impressive developments of high performance digital CMOS technologies in the last years have made possible the implementation of very complex algorithms in low cost chips. Digital signal processors, programmable devices such as FPGAs and VLSI technologies have come to the point where the computing power and the memory required to execute several real time applications can be incorporated even in cheap portable devices. Among the several application fields that have been strongly developed by this technology progress, channel decoding is one of the most significant and interesting: as predicted by Shannon, the achievement of performance close to the theoretical limit implies the adoption of high complexity algorithms, so making the search for good decoding architecture a challenging and fascinating problem for many digital architects and VLSI designers. There are a number of aspects of turbo codes that make them so interesting also from an implementation point of view: first of all the algorithms that are used to implement the MAP decoding (such as the so called BCJR algorithm) are of great complexity; this complexity, coupled with the iterative nature of the whole decoding process, makes very difficult the accomplishment of throughput, latency, cost and energy dissipation constraints imposed by several modern multimedia and interactive applications. Moreover turbo decoders include large RAM memories that need to be organized and managed properly. Finally, the decoding algorithm can be parallelized in several ways, acting at different levels and the best solution for each application can only be selected by carefully exploring the space of design alternatives.The chapter reviews all main achievements obtained in the last 10 years in the hardware implementation of turbo codes and particularly the critical aspects that designers have to deal with. The main addressed problems are the following.•

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“…A number of implementations addressed various turbo decoders achieving medium throughput figures [60], [61], [62], [56].…”

Section: Standards and Productsmentioning

confidence: 99%

VLSI for Turbo Codes

Masera

Turbo Code Applications

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1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

et al. 2016

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Iterative decoder architectures

Yeo

Anantharam

2003

IEEE Commun. Mag.

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Implementation constraints imposed on iterative decoders applying message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the decoding algorithm. Turbo codes and low-density parity check codes, in particular, are evaluated in terms of their suitability for VLSI implementation in addition to their bit-error rate performance as a function of signal-to-noise ratio. It is necessary to consider efficient realizations of iterative decoders when area, power, and throughput of the decoding implementation are constrained by practical design issues of communications receivers.

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FPGA implementation of a 3GPP turbo codec

Cited by 4 publications

References 4 publications

VLSI for Turbo Codes

VLSI for Turbo Codes

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

Iterative decoder architectures

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