2003
DOI: 10.1109/mcom.2003.1222729
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Iterative decoder architectures

Abstract: Implementation constraints imposed on iterative decoders applying message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the decoding algorithm. Turbo codes and low-density parity check codes, in particular, are evaluated in terms of their suitability for VLSI implementation in addition to their bit-error rate performance as a function of sig… Show more

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Cited by 46 publications
(1 citation statement)
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“…But the performance of CDMA (Yeo et al, 2003;Kuppusamy et al, 2008) is limited by multiple access interference and inter symbol interference. With CDMA fading is circumvented by the use of interleavers placed between FEC and spreading.…”
Section: Introductionmentioning
confidence: 99%
“…But the performance of CDMA (Yeo et al, 2003;Kuppusamy et al, 2008) is limited by multiple access interference and inter symbol interference. With CDMA fading is circumvented by the use of interleavers placed between FEC and spreading.…”
Section: Introductionmentioning
confidence: 99%