FPGA Based Sparse Matrix Vector Multiplication using Commodity DRAM Memory

Gregg, David; Sweeney, Cheryl; McElroy, Ciaran; Connor, Fergal; McGettrick, Seamas; Moloney, David; Geraghty, Dermot

doi:10.1109/fpl.2007.4380769

Cited by 20 publications

(11 citation statements)

References 10 publications

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“…Depending on the implementation, the meta-data for CSR is either pre-loaded into the bitstream or dynamically accessed from external memory. While earlier designs were restricted to on-die memory capacities (e.g., [18]), more recent designs incorporate memory hierarchies that can handle large data sets exceeding the available onchip memories [24,25,26,11,10,27,9,28,29,30,14,23].…”

Section: Related Workmentioning

confidence: 99%

Towards a Universal FPGA Matrix-Vector Multiplication Architecture

Kestur

Davis

Chung

2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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We present the design and implementation of a universal, single-bitstream library for accelerating matrixvector multiplication using FPGAs. Our library handles multiple matrix encodings ranging from dense to multiple sparse formats. A key novelty in our approach is the introduction of a hardware-optimized sparse matrix representation called Compressed Variable-Length Bit Vector (CVBV), which reduces the storage and bandwidth requirements up to 43% (on average 25%) compared to compressed sparse row (CSR) across all the matrices from the University of Florida Sparse Matrix Collection. Our hardware incorporates a runtimeprogrammable decoder that performs on-the-fly decoding of various formats such as Dense, COO, CSR, DIA, and ELL. The flexibility and scalability of our design is demonstrated across two FPGA platforms: (1) the BEE3 (Virtex-5 LX155T with 16GB of DRAM) and (2) ML605 (Virtex-6 LX240T with 2GB of DRAM). For dense matrices, our approach scales to large data sets with over 1 billion elements, and achieves robust performance independent of the matrix aspect ratio. For sparse matrices, our approach using a compressed representation reduces the overall bandwidth while also achieving comparable efficiency relative to state-of-the-art approaches.

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Section: Related Workmentioning

confidence: 99%

Towards a Universal FPGA Matrix-Vector Multiplication Architecture

Kestur

Davis

Chung

2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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“…Gregg et al [3] used a variant of CSC, dubbed the sparse matrix architecture and representation (SPAR) format [2], where the row ind and col ptr are combined into a single vector with zero padding introduced at the start of each column of data vector. David DuBois and Andrew DuBois [4] made no assumption about the structure of the sparse matrix with the exception that the implementation was designed to process up to 7 elements per row, and if any row contains fewer than 7 elements it must be padded with zeros to the full 7 elements.…”

Section: Introductionmentioning

confidence: 99%

Greedy Approach Based Heuristics for Partitioning Sparse Matrices

Huang

Ren

2015

IEICE Trans. Inf. & Syst.

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SUMMARYSparse Matrix-Vector Multiplication (SpMxV) is widely used in many high-performance computing applications, including information retrieval, medical imaging, and economic modeling. To eliminate the overhead of zero padding in SpMxV, prior works have focused on partitioning a sparse matrix into row vectors sets (RVS's) or sub-matrices. However, performance was still degraded due to the sparsity pattern of a sparse matrix. In this letter, we propose a heuristics, called recursive merging, which uses a greedy approach to recursively merge those row vectors of nonzeros in a matrix into the RVS's, such that each set included is ensured a local optimal solution. For ten uneven benchmark matrices from the University of Florida Sparse Matrix Collection, our proposed partitioning algorithm is always identified as the method with the highest mean density (over 96%), but with the lowest average relative difference (below 0.07%) over computing powers. key words: partitioning, greedy approach, recursive merging, highest mean density, lowest average relative difference

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“…For sparse-matrix vector multiplication kernel, a data reordering scheme was presented in [7]. This data reordering scheme improved the cache-misses when accessing the vector elements from the external memory.…”

Section: A Related Workmentioning

confidence: 99%

“…There has been work in using external memory for other BLAS kernels on FPGA [7], [5]. For sparse-matrix vector multiplication kernel, a data reordering scheme was presented in [7].…”

Section: A Related Workmentioning

confidence: 99%

Energy-efficient large-scale matrix multiplication on FPGAs

Matam

Prasanna

2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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Abstract-Energy efficiency has emerged as one of the key performance metrics in computing. In this work, we present an energy efficient design for large-scale matrix multiplication. As a baseline architecture, we use a highly optimized on-chip matrix multiplication architecture extended to support large matrices using external memory. Based on the matrix multiplication algorithm and the DRAM model, we present an efficient data layout for storing the input matrices. This data layout reduces the energy consumed by the external memory by minimizing the number of row activations in a DRAM. By exploiting the matrix multiplication algorithm, modular structure of the DRAM, and the high bandwidth between the on-chip and the external memory, we propose a memory activation schedule. This memory activation schedule is based on a realistic DRAM model and reduces the memory energy, which is the dominant energy of the design. Our proposed scheme improves the energy efficiency (defined as the number of operations per Joule) of the baseline architecture by 1.6×, 1.3×, and 1.2× for 32K×32K 16-bit fixed point, 32K×32K single precision floating point, and 16K×16K double precision floating point matrix multiplication, respectively.

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FPGA Based Sparse Matrix Vector Multiplication using Commodity DRAM Memory

Cited by 20 publications

References 10 publications

Towards a Universal FPGA Matrix-Vector Multiplication Architecture

Towards a Universal FPGA Matrix-Vector Multiplication Architecture

Greedy Approach Based Heuristics for Partitioning Sparse Matrices

Energy-efficient large-scale matrix multiplication on FPGAs

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