FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining Applications

Perera, Darshika G.; Li, Kin Fun

doi:10.1109/3pgcic.2011.25

Cited by 25 publications

(31 citation statements)

References 6 publications

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“…For our previous proof-of-concept experiments [32], the data were read directly from the DDR3-SDRAM, processed, and the intermediate/final results were written back to the SDRAM. This external memory access latency incurred a significant performance bottleneck.…”

Section: Results and Analysis For Srh And Drhmentioning

confidence: 99%

“…From our proof-of-concept work [32], it was observed that a significant amount of time was spent on accessing DDR3-SDRAM external memory, which was a major performance bottleneck. For the current system-level design, in addition to the AXI Master Burst, we designed and incorporated a pre-fetching technique to our userdesigned hardware (in Fig.…”

Section: Pre-fetching Techniquementioning

confidence: 99%

“…It should be noted that we only designed the first two stages of the PCA computation in our previous work [32]. For this research work, we are using single precision floating-point operations for all four stages of the PCA computations.…”

Section: Embedded Reconfigurable Hardware Designmentioning

confidence: 99%

“…For our proof-of-concept work [32], we modified the above two equations slightly in order to use integer operations for the mean and covariance matrix computations. It should be noted that we only designed the first two stages of the PCA computation in our previous work [32].…”

Section: Embedded Reconfigurable Hardware Designmentioning

confidence: 99%

“…The ML605 board utilizes a Xilinx Virtex 6 XC6VLX240T-FF1156 device. The development platform includes large on-chip logic resources (37, As a proof-of-concept work [31,32], we initially proposed reconfigurable hardware support for the first two stages of the PCA computation, where both the SRH [31] and the DRH [32] are designed using integer operators. Unlike our proof-of-concept designs, in this research work, both the software and hardware modules are designed using floating-point operators, instead of integer operators.…”

Section: Design Approach and Development Platformmentioning

confidence: 99%

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Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

Shahrouzi

Perera

2017

J Embedded Systems

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With the advancement of mobile and embedded devices, many applications such as data mining have found their way into these devices. These devices consist of various design constraints including stringent area and power limitations, high speed-performance, reduced cost, and time-to-market requirements. Also, applications running on mobile devices are becoming more complex requiring significant processing power. Our previous analysis illustrated that FPGA-based dynamic reconfigurable systems are currently the best avenue to overcome these challenges. In this research work, we introduce efficient reconfigurable hardware architecture for principal component analysis (PCA), a widely used dimensionality reduction technique in data mining. For mobile applications such as signature verification and handwritten analysis, PCA is applied initially to reduce the dimensionality of the data, followed by similarity measure. Experiments are performed, using a handwritten analysis application together with a benchmark dataset, to evaluate and illustrate the feasibility, efficiency, and flexibility of reconfigurable hardware for data mining applications. Our hardware designs are generic, parameterized, and scalable. Furthermore, our partial and dynamic reconfigurable hardware design achieved 79 times speedup compared to its software counterpart, and 71% space saving compared to its static reconfigurable hardware design.

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Section: Results and Analysis For Srh And Drhmentioning

confidence: 99%

Section: Pre-fetching Techniquementioning

confidence: 99%

Section: Embedded Reconfigurable Hardware Designmentioning

confidence: 99%

Section: Embedded Reconfigurable Hardware Designmentioning

confidence: 99%

Section: Design Approach and Development Platformmentioning

confidence: 99%

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Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

Shahrouzi

Perera

2017

J Embedded Systems

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A Hardware Collective Intelligence Agent

Perera

2013

Transactions on Computational Collective Intelligence X

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Electronic nose system on the Zynq SoC platform

Ali

Djelouat

Amira

et al. 2017

Microprocessors and Microsystems

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Electronic nose or machine olfaction are systems used for detection and identification of odorous compounds and gas mixtures. An electronic nose system is mainly made of two parts, the sensing part which takes the form of a single or a set of sensors and the processing part which takes the form of some pattern recognition algorithms. As an alternative solution to pure software or hardware implementation of the processing part of a gas identification system, this paper proposes a hardware/software co-design approach using the Zynq platform for the implementation of an electronic nose system based on principal component analysis as a dimensionality reduction technique and decision tree as a classification algorithm using two different sensors array, a 4 × 4 in-house fabricated sensor and a commercial one based on 7 Figaro sensors, for comparison purpose. The system was successfully trained and simulated in MATLAB environment prior to the implementation on the Zynq platform. Various scenarios were explored and discussed including the investigation of different combination of principal components as well as the utilization of drift compensation technique to improve the identification accuracy. High level synthesis was carried out on the proposed designs using different optimization directives including loop unrolling, array partitioning and pipelining. Hardware implementation results on the Zynq system on chip show that real-time performances can be achieved for proposed EN systems using hardware/software co-design approach with a single ARM processor running at 667 MHz and the programmable logic running at 142 MHz. In addition, using the designed IP cores and for the best scenarios, a gas can be identified in 3.46 µs using the 4 × 4 sensor and 0.55 µs using the Figaro sensors. Furthermore, it has been noticed that the choice of the sensor array has an important impact on performances in terms of accuracy and processing time. Finally, it has been demonstrated that the programmable logic of the Zynq platform consumes much less power than the processing system.

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FPGA-Based Reconfigurable Hardware for Compute Intensive Data Mining Applications

Cited by 25 publications

References 6 publications

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

A Hardware Collective Intelligence Agent

Electronic nose system on the Zynq SoC platform

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