FPGA-Based Real-Time Implementation of Bivariate Empirical Mode Decomposition

Abstract

A Field Programmable Gate Array (FPGA) based parallel architecture for the real-time and online implementation of the bivariate extension of the empirical mode decomposition (EMD) algorithm is presented. Multivariate extensions of EMD have attracted significant attention in recent years owing to their scope in applications involving multichannel and multidimensional data processing, e.g. biomedical engineering, condition monitoring, image fusion. However, these algorithms are computationally expensive due to the empirical and data-driven nature of these methods. That has hindered the utilisation of EMD, and particularly its bivariate and multivariate extensions, in realtime applications. The proposed parallel architecture is aimed at bridging this gap through real-time computation of the bivariate EMD algorithm. The crux of the architecture is the simultaneous computation of multiple signal projections, locating their local extrema and finally the calculation of their associated complex valued envelopes for the estimation of local mean. The architecture is implemented on a Xilinx Kintex 7 FPGA, and offers significant computational improvements over the existing software based sequential implementaions of bivariate EMD.

An efficient hardware realization of EMD for real‐time signal processing applications

“…The highest sampling and clock rate obtained by the method (FPGA-based) proposed by us is 50 MHz. The sampling rate of our proposed method is higher than the methods proposed in Hong et al 18 and Malik et al 23 Cagdas et al 12 and Chen et al 16 did not mention their sampling rate. The sampling rate is important because the greater the sampling rate, the higher the frequency in a signal the design is able to process (fs ≥ 2fm, fs is the sampling frequency and fm is the maximum frequency of the signal).…”

“…The sampling rate is important because the greater the sampling rate, the higher the frequency in a signal the design is able to process (fs ≥ 2fm, fs is the sampling frequency and fm is the maximum frequency of the signal). The sampling frequency in case of Malik et al 23 was 25 MHz, whereas in our case, sampling frequency is 50 MHz, which means our design can process higher frequency signals. The execution time of the design (using STI) proposed in Hong et al 18 and Chen et al 16 is more than the execution time of our proposed design using LBC (same functionality as STI).…”

“…To create a suitable IMF, S should be taken as between 3 and 5. 23,24 (2) A layout design of the proposed EMD is done up to placement and routing (PnR). The layout has small core area and has less power consumption.…”

FPGA and ASIC realisation of EMD algorithm for real‐time signal processing

“…The motivation behind the use of this criterion is its simplicity and can be used in EMD for its real‐time implementation. It is observed that S varies between 3 and 5 to produce a good IMF [17, 18]. (ii) Here, we have used two envelope generation techniques one with CSI and other one is using ST interpolation (STI) followed by a moving average (MOVAVG) module.…”

“…The motivation behind the use of this criterion is its simplicity and can be used in EMD for its real‐time implementation. It is observed that S varies between 3 and 5 to produce a good IMF [17, 18].…”