FPGA based performance analysis of multiplier policies for FIR filter

Pathan, Ashfaque Ahmed; Memon, Tayab Din; Keerio, Sharmeen; Kalwar, Imtiaz Hussain

doi:10.1109/icaees.2016.7888001

Cited by 14 publications

(5 citation statements)

References 8 publications

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“…The main blocks of the filter are multiplier, adder, and a delay block. 1 The multiplier multiplies input with the coefficients; adder adds the outputs from delay block and multipliers. The linear phase filters are positive or negative symmetry depending on M, as shown below equation.…”

Section: Fir Filter W I T H Windowing Techniquementioning

confidence: 99%

See 1 more Smart Citation

Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

Hussain

Parvin²

2020

SMSJ

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This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A comparison between three different windows has been made. The FIR is designed in MATLAB using a windowing technique. Then it is synthesized on Xilinx 14.7, Virtex 6 XC6VLX760, whose results are included in this paper.

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Section: Fir Filter W I T H Windowing Techniquementioning

confidence: 99%

“…Their application can also be found in intensive care units where a large number of wired and wireless electronic devices must coexist. 1 The basic block diagram of a digital communication system is shown in Figure 1. SDR is used to implement the digital part.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

Hussain

Parvin²

2020

SMSJ

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“…In image processing, filtering transformations and other operations need complex multiplications, and the multiplier is one of the most resources consuming elements [7,8]. The research proposes various traditional and nontraditional multiplier optimization methods and schemes and implements software based or on hardware (ASICS and FPGAs) [9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Computationally efficient low-power sigma delta modulation-based image processing algorithm

Pathan,

Memon,

Memon

et al. 2023

Mehran Univ. res. j. eng. technol.

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Digital Image Processing has dominated Digital Signal Processing at the cost of more memory, resources, and high computational power. In image processing, filtering transformations and other operations need complex multiplications, and the multiplier is one of the most resources consuming elements. Recently, mitigating the multiplier complexity in the digital signal processing (DSP) algorithms sigma-delta modulation based general purpose and adaptive DSP algorithms are developed in MATLAB and compared with its counterpart multi-bit algorithms for functionality and area-performance-power in FPGA. The contemporary multiplier algorithms are also optimized to overcome the multiplier complexity challenge as computation becomes simple and fast. This paper extends the reported work by investigating the sigma-delta modulation approaches for developing a computationally efficient low-power image processing algorithm. The proposed model is designed, developed, and simulated in MATLAB. The simulation results are analyzed using SNR, MSE, and Peak SNR. The simulation results show that the proposed system can better mitigate the noise effect, making it robust for noisy environment.

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“…In DSP algorithm optimization, a major bottleneck is the multiplier complexity that is evident for example in FIR, IIR, FFT, etc. Despite current optimization proposals, multiplier implementations still take more area and consume more power and observe delay [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Analysis of Existing and Proposed 3-Bit and Multi-Bit Multiplier Algorithms for FIR Filters and Adaptive Channel Equalizers on FPGA

Pathan

Memon

Sohu

et al. 2021

QUEST Research Journal

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Different multiplication algorithms have different performance characteristics. Some are good at speed while others consume less area when implemented on hardware, like Field Programmable Gate Array (FPGA)-the advanced implementation technology for DSP systems. The eminent parallel and sequential multiplication algorithms include Shift and Add, Wallace Tree, Booth, and Array. The multiplier optimization attempts have also been reported in adders used for partial product addition. In this paper, analogous to conventional multipliers, two new multiplication algorithms implemented on FPGA are shown and compared with conventional algorithms as stand-alone and by using them in the implementation of FIR filters and adaptive channel equalizer using the LMS algorithm. The work is carried out on Spartan-6 FPG that may be extended for any type of FPGA. Results are compared in terms of resource utilization, power consumption, and maximum achieved frequency. The results show that for a small length of coefficients like 3-bit, the proposed algorithms work very well in terms of achieved frequency, consumed power, and even resource utilization. Whilst for the length greater than 3-bit, the Pipelined multiplier is much better in frequency than the proposed and conventional ones, and the Booth multiplier consumes fewer resources in terms of lookup tables.

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FPGA based performance analysis of multiplier policies for FIR filter

Cited by 14 publications

References 8 publications

Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

Computationally efficient low-power sigma delta modulation-based image processing algorithm

Analysis of Existing and Proposed 3-Bit and Multi-Bit Multiplier Algorithms for FIR Filters and Adaptive Channel Equalizers on FPGA

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