FPGA-Based Multimodal Embedded Sensor System Integrating Low- and Mid-Level Vision

Botella, Guillermo; Martı́n, Humberto; Santos, Matilde; Meyer-Baese, Uwe

doi:10.3390/s110808164

Cited by 29 publications

(22 citation statements)

References 38 publications

(52 reference statements)

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“…The research papers [19][20][21] on methods for motion estimation on a customizable reconfigurable hardware motivate the researchers to search for biologically inspired FFT architectures which might provide the best solution to design a low power FFT. To achieve low power implementation of DSP circuits, pipelining, parallel processing, algebraic transformations, and algorithmic modifications are generally employed [10].…”

Section: Low Power Fft Architectures and Techniquesmentioning

confidence: 99%

Low power reconfigurable FP-FFT core with an array of folded DA butterflies

Paul

Raju²,

Janakiraman³

2014

EURASIP J. Adv. Signal Process.

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A variable length (32~2,048), low power, floating point fast Fourier transform (FP-FFT) processor is designed and implemented using energy-efficient butterfly elements. The butterfly elements are implemented using distributed arithmetic (DA) algorithm that eliminates the power-consuming complex multipliers. The FFT computations are scheduled in a quasi-parallel mode with an array of 16 butterflies. The nodes of the data flow graph (DFG) of the FFT are folded to these 16 butterflies for any value of N by the control unit. Register minimization is also applied after folding to decrease the number of scratch pad registers to (log 2 N − 1) × 16. The real and imaginary parts of the samples are represented by 32-bit single-precision floating point notation to achieve high precision in the results. Thus, each sample is represented using 64 bits. Twiddle factor ROM size is reduced by 25% using the symmetry of the twiddle factors. Reconfigurability based on the sample size is achieved by the control unit. This distributed floating point arithmetic (DFPA)-based design of FFT processor implemented in 45-nm process occupies an area of 0.973 mm 2 and dissipates a power of 68 mW at an operating frequency of 100 MHz. When compared with FFT processor designed in the same technology with multiplier-based butterflies, this design shows 33% less area and 38% less power. The throughput for 2,048-point FFT is 222 KS/s and the energy spent per FFT is 7.4 to 14 nJ for 64 to 2,048 points being one among the most energy-efficient FFT processors.

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Section: Low Power Fft Architectures and Techniquesmentioning

confidence: 99%

Low power reconfigurable FP-FFT core with an array of folded DA butterflies

Paul

Raju²,

Janakiraman³

2014

EURASIP J. Adv. Signal Process.

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“…In recent years, several improvements have been proposed to the classical optical flow estimators. Some of them proposed bioinspired optical flow VLSI implementations on embedded hardware [8,9], FPGAs [10][11][12] or GPUs [13]. Due to temporal restrictions in most applications, some of the methods proposed relaxed versions of the algorithm to accelerate its processing [14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Real time motion estimation using a neural architecture implemented on GPUs

García-Rodríguez

Orts-Escolano

Angelopoulou

et al. 2014

J Real-Time Image Proc

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This work describes a neural network based architecture that represents and estimates object motion in videos. This architecture addresses multiple computer vision tasks such as image segmentation, object representation or characterization, motion analysis and tracking. The use of a neural network architecture allows for the simultaneous estimation of global and local motion and the representation of deformable objects. This architecture also avoids the problem of finding corresponding features while tracking moving objects. Due to the parallel nature of neural networks, the architecture has been implemented on GPUs that allows the system to meet a set of requirements such as: time constraints management, robustness, high processing speed and re-configurability. Experiments are presented that demonstrate the validity of our architecture to solve problems of mobile agents tracking and motion analysis.

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“…In [14], low complexity and low energy adaptive hardware for H.264 with multiple frame reference motion estimation is proposed and implemented on an FPGA platform. A bioinspired custom-made reconfigurable hardware architecture is proposed in [15,16] for efficient computation of motion between image sequences. The work in [17] proposed a flexible and scalable fast estimation processor targeting the computational requirements for high definition video using the H.264 video codec on an FPGA platform.…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based Portable Ultrasound Scanning System with Automatic Kidney Detection

et al. 2015

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Bedsides diagnosis using portable ultrasound scanning (PUS) offering comfortable diagnosis with various clinical advantages, in general, ultrasound scanners suffer from a poor signal-to-noise ratio, and physicians who operate the device at point-of-care may not be adequately trained to perform high level diagnosis. Such scenarios can be eradicated by incorporating ambient intelligence in PUS. In this paper, we propose an architecture for a PUS system, whose abilities include automated kidney detection in real time. Automated kidney detection is performed by training the Viola–Jones algorithm with a good set of kidney data consisting of diversified shapes and sizes. It is observed that the kidney detection algorithm delivers very good performance in terms of detection accuracy. The proposed PUS with kidney detection algorithm is implemented on a single Xilinx Kintex-7 FPGA, integrated with a Raspberry Pi ARM processor running at 900 MHz.

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FPGA-Based Multimodal Embedded Sensor System Integrating Low- and Mid-Level Vision

Cited by 29 publications

References 38 publications

Low power reconfigurable FP-FFT core with an array of folded DA butterflies

Low power reconfigurable FP-FFT core with an array of folded DA butterflies

Real time motion estimation using a neural architecture implemented on GPUs

FPGA-Based Portable Ultrasound Scanning System with Automatic Kidney Detection

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