FPGA-based multi-channel data acquisition system for Superheated Emulsion Detectors

Sahoo, Shantonu; Chaddha, Niraj; Sahoo, Sunita; Biswas, Nilanjan; Roy, Anindya; Das, Mala; Pal, Sarbajit

doi:10.1016/j.nima.2021.165457

Cited by 8 publications

(5 citation statements)

References 15 publications

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“…A similar approach was taken in [15], a design of a DAQ system developed for Superheated Emulsion Detectors (SEDs) [16]. The paper presents a 10-channel, 12-bit resolution high-speed DAQ system with acquisition rates of 500 kSps per channel.…”

Section: Fpga-based Fast Daq Systemsmentioning

confidence: 98%

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High Performance Software Architectures for Remote High-Speed Data Acquisition

Turkmanović,

Karličić,

Rajović

et al. 2023

Electronics

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There are various tools for real-time data acquisition and analysis of high-frequency signals. Usually, the tools for data acquisition and analysis are incompatible with each other, expensive, or require the utilization of various technologies. Designing a unique toolset for real-time data acquisition and analysis of high-frequency signals presents a large challenge, both in terms of hardware and software design. Some of the main challenges include fulfilling strict real-time performance requirements, using cost-effective hardware components, and designing a software architecture with minimal software latency for data sampling on an embedded platform and data analysis on a PC machine. This paper presents a software architecture design methodology for embedded platforms, including an RTOS and an Ethernet interface, along with the application architecture on the host side. To demonstrate the advantages of the proposed methodology, a prototype consisting of the STM32H747 microcontroller, FreeRTOS operating system, and a GUI application based on the Qt framework has been created. It has been shown that using the proposed architecture design methodology makes it possible to preserve the maximal hardware sampling rate utilizing a 100 Mbps Ethernet link. In the experiments, sampling rates up to 4.57 MSps for 10-bit resolution and real-time transfer of data over Ethernet link and visualization on host PC have been achieved with this specific MCU.

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Section: Fpga-based Fast Daq Systemsmentioning

confidence: 98%

“…The Channel component from Figure 2 can have many different forms, wired or wireless, or a combination of the two; it could connect a Host and a Source on the same board [11,22], within a chassis [12], within a facility [15,35,36], or even at different continents.…”

Section: The Communication Channelmentioning

confidence: 99%

High Performance Software Architectures for Remote High-Speed Data Acquisition

Turkmanović,

Karličić,

Rajović

et al. 2023

Electronics

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“…In fact, the development of an efficient infrastructure for data communication is a common problem addressed by the work plans of all major facilities and international projects supporting large-scale scientific experiments. For example, several works that have appeared in the literature in recent years involve interconnects for data communication in high-energy physics (HEP), e.g., for the Large Hadron Collider (LHC) at CERN [1,3], data acquisition from 2D X-ray detectors in the RASHPA platform at the European Synchrotron Radiation Facility (ESRF) [6], from gain adaptive detectors used for macromolecular crystallography [8], or from superheated emulsion detectors, e.g., based on FPGA multi-channel acquisition systems [9], as well as projects dealing with astronomic data, including the Square Kilometer Area (SKA) telescope [4] or specific applications such as adaptive optics [5].…”

Section: Background and Key Technologiesmentioning

confidence: 99%

“…The work in [12] compares the network performance of FPGAs against bare-metal servers, virtual machines, and Linux containers, finding improved round trip times and throughput levels for the case of FPGAs. The authors of [9] present a dedicated FPGA-based multi-channel data acquisition system for superheated emulsion detectors developed as a standalone, portable component to be connected to a PC through a UART link.…”

Section: Background and Key Technologiesmentioning

confidence: 99%

“…At the same time, these applications pose unprecedented processing requirements for the vast amount of data being generated and transferred, increasingly leading to the adoption of accelerator-based platforms, e.g., using graphics processing units (GPUs) or field-programmable gate arrays (FPGAs) in order to meet stringent energy-efficiency requirements through some form of customized computing. Consequently, many very recent works have explored advanced solutions for improving the end-to-end data communication performance targeting accelerator-based platforms, particularly those based on customized FPGA accelerators, in the context of scientific data acquisition and scientific computing [3,[5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

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Evaluation of HPC Acceleration and Interconnect Technologies for High-Throughput Data Acquisition

Cilardo

2021

Sensors

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Efficient data movement in multi-node systems is a crucial issue at the crossroads of scientific computing, big data, and high-performance computing, impacting demanding data acquisition applications from high-energy physics to astronomy, where dedicated accelerators such as FPGA devices play a key role coupled with high-performance interconnect technologies. Building on the outcome of the RECIPE Horizon 2020 research project, this work evaluates the use of high-bandwidth interconnect standards, namely InfiniBand EDR and HDR, along with remote direct memory access functions for direct exposure of FPGA accelerator memory across a multi-node system. The prototype we present aims at avoiding dedicated network interfaces built in the FPGA accelerator itself, leaving most of the resources for user acceleration and supporting state-of-the-art interconnect technologies. We present the detail of the proposed system and a quantitative evaluation in terms of end-to-end bandwidth as concretely measured with a real-world FPGA-based multi-node HPC workload.

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Optimization design of high-speed data acquisition system based on DMA double cache mechanism

Zhou

Yang

2022

Microelectronics Journal

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FPGA-based multi-channel data acquisition system for Superheated Emulsion Detectors

Cited by 8 publications

References 15 publications

High Performance Software Architectures for Remote High-Speed Data Acquisition

High Performance Software Architectures for Remote High-Speed Data Acquisition

Evaluation of HPC Acceleration and Interconnect Technologies for High-Throughput Data Acquisition

Optimization design of high-speed data acquisition system based on DMA double cache mechanism

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