FPGA-Based Modeling and Design Methodology of a Digital Pre-distortion System for Power Amplifier Linearization

Juarez-Cazares, S A; Melendez-Cano, Ashley; Cárdenas-Valdez, José Ricardo; Galaviz-Aguilar, José Alejandro; Vazquez-Lopez, C E; Roblin, Patrick; Nuñez-Perez, Jose-Cruz

doi:10.1109/icmeae.2016.029

Cited by 4 publications

(1 citation statement)

References 14 publications

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“…A look-up-table (LUT) based memory polynomial model is proposed in [16]- [17] for DPD. They used a fixed sample set of the input signal for hardware verification without any real-time adaptability.…”

Section: State-of-the-artmentioning

confidence: 99%

Software-Defined Radio Transceiver Design Using FPGA-Based System-on-Chip Embedded Platform With Adaptive Digital Predistortion

Kumar

Rawat

2020

IEEE Access

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In this paper, a software-defined radio (SDR) based transceiver system is designed and implemented on the system-on-chip (SoC) platform, which consists of a high-speed Arm embedded processor and a reconfigurable field-programmable gate array (FPGA). In the proposed SDR transceiver, the real-time baseband signal generation and adaptive digital predistortion (ADPD) units are implemented on the SoC platform. Memory polynomial model based ADPD solution is implemented to linearize the radio frequency (RF) power amplifiers (PAs). The implementation of the ADPD on a reconfigurable FPGA platform makes the system flexible and cost-effective. The PA characterization, in terms of model extraction and coefficient calculation, is done in real-time. These calculated coefficients are updated in the transmission path to precondition the transmitted signal before it is applied to the PA. The proposed ADPD is applied at the baseband level. Therefore, it can be used for different classes of PA operating at different RF carrier frequencies. A long-term evolution (LTE) signal with 20 MHz bandwidth and 11 dB peak to average power ratio (PAPR) is used for simulation and measurement purposes. The LTE signal is amplified using a GaN-based harmonically tuned continuous Class-F PA in measurement. The performance of the implemented ADPD scheme is analyzed in terms of NMSE, ACPR and EVM. INDEX TERMS Digital predistortion, field-programmable gate array, linearization, memory polynomial, software-defined radios, system-on-chip, transceiver. I. INTRODUCTION As technology is growing, advanced wireless communication devices have become an essential part of the everyone's daily life. These communication devices require high-speed access for voice, video, data and other such applications [1]-[3]. The commercial wireless communication standards are upgraded from 2 nd generation (2G) to 5 th generation (5G) and each generation uses different network protocols and different communication standards [3]. Therefore, all communication devices need to be updated whenever a new generation of wireless communication standard is introduced [3]. Modifying communication devices for different communication standards is a critical and costly affair. Therefore, the demand for a flexible, reconfigurable and programmable communication system that can be easily modified without any hardware cost has been increasing significantly. Software-defined radio (SDR) is a favorable solution to solve such problems. SDR is a rapidly developing technology in the telecommunication industry to develop a flexible and reconfigurable transceiver architecture. SDRs can upgrade their functionality without replacing the hardware on which they are implemented [4] [5]. This feature supports SDR to develop a multifunctionality transceiver device that is suitable for any type of communication standard. Such SDR based programmable communication devices can handle the existing as well as the newly developed wireless communication standards and network protocols. In SDRs, baseband signal proces...

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Section: State-of-the-artmentioning

confidence: 99%