FPGA based implementation of baseline JPEG decoder

Ahmad, Jamshaid; Raza, Kamran; Ebrahim, Mansoor; Talha, Syed Muhammad Umar

doi:10.1145/1838002.1838035

Cited by 15 publications

(9 citation statements)

References 20 publications

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“…Percent share of screen resolution in Europe market [3] Since its very popular in image compression many software and hardware techniques have been developed to improvise the speed of JPEG decoding process. To the hardware resources for the JPEG decoder, Some common efficient ways can be obtained using the ,FPGA (Field Programmable Gate Array) or other ASIC (Application Specific Integrated Circuit) resources, DSP (Digital Signal Processor) [2].With increasing computations speed of GPU along with the CUDA framework a software decoder can be efficiently implemented.…”

Section: Introductionmentioning

confidence: 99%

Acceleration of JPEG Decoding Process using CUDA

Tade¹,

Ansari²

2015

IJCA

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In this paper we have implemented efficient JPEG (Joint Photographic experts group) Decoder on GPU (Graphic Processing Unit) using NVIDIA CUDA (Compute Unified Device Architecture) Technology. This decoder is capable of decoding images of Ultra HD resolution with superfast speed GPU is used to assist the CPU for time consuming tasks. In this paper IDCT module which consumes 70 to 80 percent of computation time is implemented on GPU. An asynchronous parallel execution between the CPU and the GPU is used at a same time to improve the JPEG decoder acceleration rate. In this work, the JPEG decoder based on the CUDA performs decompression of images of size 2560 x 1600 pixels and below. Finally the results are shown with respect to different sized images and consumed time for decoding. The results show that this decoder faster in multiple times than the decoder in CPU.

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Section: Introductionmentioning

confidence: 99%

Acceleration of JPEG Decoding Process using CUDA

Tade¹,

Ansari²

2015

IJCA

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“…In [5], the JPEG algorithm with Artificial Neural Network (ANN) is implemented in Verilog HDL & supporting software in MATLAB on DSP board, achieving significant compression ratios. There is another paper [6], which designed FPGA based High speed, low power, low complexity Baseline JPEG Decoder only, where decoding of Baseline JPEG color and gray images is achieved. There are other research papers [7, 8 & 9] which focus only on the implementation of some of the stages of JPEG compression algorithm like 2D-DCT, quantization or Huffman coding onto the FPGAs.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Variable Quality Factor JPEG Image Compression Using Dynamic Partial Reconfiguration and Microblaze

Sarkhawas¹,

Khandekar²,

Kulkarni³

2015

2015 International Conference on Computing Communication Control and Automation

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As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an attractive feature of FPGA, which has opened up new directions for researchers. This feature allows multiple functions to time-share the FPGA resources by exploiting reconfigurable area more efficiently. This paper designs a system using the high performance, high capacity Virtex-4 FPGA for hardware acceleration of JPEG Image Compression Algorithm along with Microblaze and Dynamic Partial Reconfigurable (DPR) using Xilinx's PlanAhead tool to achieve on-the-fly multiple Quality Factors (Q) of the compressed images corresponding to different Image Qualities and sizes in varying application scenarios.

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“…To the hardware resources for the JPEG decoder, Some common efficient ways can be obtained using the DSP (Digital Signal Processor),FPGA (Field Programmable Gate Array) or other ASIC (Application Specific Integrated Circuit) resources [2]. To the software for the JPEG decoder, with the rapid increase of the computation speed of the GPU in days and the emergence of the CUDA technology, a software solution method can be proposed by using the CUDA technology and it can save more hardware resources and make up the low programmability of hardware.…”

Section: Introductionmentioning

confidence: 99%

CUDA-based acceleration of the JPEG decoder

Shan

Yang

2013

2013 Ninth International Conference on Natural Computation (ICNC)

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In this paper, an accelerated JPEG(Joint Photographic Experts Group) decoder was efficiently implemented on the GPU(Graphic Processing Unit) using the CUDA(Computer Unified Device Architecture) technology and it is capable for high definition images decoding. The CUDA technology can assist the GPU to work for the CPU for large computation. In this paper, the IDCT(Inverse Discrete Cosine Transform) model which has consumed about 75% the total time in the JPEG decoder is worked in the GPU by the CUDA, and other models of the JPEG decoder are designed in the CPU. At the same time, we use the asynchronous parallel execution between the CPU and the GPU to improve the JPEG decoder acceleration rate. In the experiment, the JPEG decoder based on the CUDA performs decompression of 3240 x 2160 pixels images, the implementation of the CUDA-based IDCT can be more than 49 times faster than the implementation on the CPU and the total processing time of the whole JPEG decoder can save about 50% time than the CPU.

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FPGA based implementation of baseline JPEG decoder

Cited by 15 publications

References 20 publications

Acceleration of JPEG Decoding Process using CUDA

Acceleration of JPEG Decoding Process using CUDA

Variable Quality Factor JPEG Image Compression Using Dynamic Partial Reconfiguration and Microblaze

CUDA-based acceleration of the JPEG decoder

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