Sericulture (silk production) is a major occupation of rural community. Producing about 15% share of the world silk produce, India is the 2nd largest silk producer after China whose total produce amounts to a staggering 80%. Analysis of sericulture practices in India shows a clear need of automation especially during pre-cocoon stages. The silkworms undergo crucial bodily changes that determine the quality as well as quantity of the silk produce, during this phase. Maintenance of optimum values of abiotic factors, like temperature, humidity etc. thus yields a dramatic change in quantity and quality of silk produce. An Intelligent Sericulture plant automation system, using zone-based cascade control of physical parameters can be one of the solutions. Currently, such systems for pre-cocoon stages are purely manual, crude, and lack intelligence. The system comprises of a data acquisition sub-system corresponding to the predetermined zones for the rearing unit, an intelligent master controller facility, data repository of past corrective actions, and cheap actuators like fans, bulbs in the zones. The master control facilitates the optimum corrective action and directs the decisions to the identified actuator sub-system based on abiotic data obtained from the respective data acquisition subsystem. The actuator sub-system achieves the corrective measures using the actuators placed in that zone of the unit. A continuous real-time feedback facilitates accurate and quick implementation of corrective steps. The system aims for increased quantity and quality of silk which is determined by reeling factor, holding capacity, roughness of silk. Also, the zonebased implementation decreases production and maintenance cost making it suitable for rural usage.
As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an attractive feature of FPGA, which has opened up new directions for researchers. This feature allows multiple functions to time-share the FPGA resources by exploiting reconfigurable area more efficiently. This paper designs a system using the high performance, high capacity Virtex-4 FPGA for hardware acceleration of JPEG Image Compression Algorithm along with Microblaze and Dynamic Partial Reconfigurable (DPR) using Xilinx's PlanAhead tool to achieve on-the-fly multiple Quality Factors (Q) of the compressed images corresponding to different Image Qualities and sizes in varying application scenarios.
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