FPGA Based High Performance Double-Precision Matrix Multiplication

Abstract

We present two designs (I and II) for IEEE 754 double precision floating point matrix multiplication, optimized for implementation on high-end FPGAs. It forms the kernel in many important tile-based BLAS algorithms, making an excellent candidate for acceleration. The designs, both based on the rank-1 update scheme, can handle arbitrary matrix sizes, and are able to sustain their peak performance except during an initial latency period. Through these designs, the trade-offs involved in terms of local-memory and bandwidth for an FPGA implementation are demonstrated and an analysis is presented for the optimal choice of design parameters. The designs, implemented on a Virtex-5 SX240T FPGA, scale gracefully from 1 to 40 processing elements(PEs) with a less than 1% degradation in the design frequency of 373 MHz. With 40 PEs and a design speed of 373 MHz, a sustained performance of 29.8 GFLOPS is possible with a bandwidth requirement of 750 MB/s for design-II and 5.9 GB/s for design-I. This compares favourably with both related art and general purpose CPU implementations.

High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication

“…They obtain a performance of 2.06 GFLOPS for a 1K by 1K matrix multiply on a Cray XD1 accelerator. Kumar et al [4] use a rank-1 update scheme to implement parallel processing elements. Sub blocks of the matrices are streamed to the architecture and intermediate results are accumulated, allowing communication and computation overlap.…”

FPGA accelerator for floating-point matrix multiplication

“…[9] uses an algorithm for scheduling input data to processing elements which has the same loop execution order as that of Zhuo and Prasanna [8]. However, instead of a systolic array-like structure (in which every PE communicates only with the adjacent ones), it uses broadcast to distribute the same elements of the first matrix simultaneously to all PEs.…”

“…Work of Kumar et al. [9] is more recent, and use FPGAs with 25x18 multipliers. In spite of that, their floating-point multiplier design require 13 such blocks.…”

“…[7]. Zhuo and Prasanna [8] describe three floating-point multiplier and adder implementations with different level of IEEE standard compliance: the "fully-compliant", "moderately-compliant" (similar to those in [7] and [9]) and "least-compliant" (which, in addition to the absence of denormal support, also lack all the rounding modes except "round toward zero" and does not generate exceptions). They specify the number of pipeline stages, area, and clock frequency for adders and multipliers using all three level of compliance.…”

“…However, the more useful measure of accelerator performance is the time necessary to multiply two matrices of given size. According to Algorithm 2, the accelerator can multiply matrices X and Y in T comp = i×j×k×n The Algorithm 1 is equivalent to the third algorithm from [8], and algorithms from [7] and [9] when they use minimal local memory size of Ω(k 2 ) words. They have the constant bandwidth requirements of B HD =3 and B FD =2 words per clock cycle.…”